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Thu, 11 Jul 2024 06:27:45 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46B6RijT020417 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 Jul 2024 06:27:44 GMT Received: from [10.216.38.48] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 10 Jul 2024 23:27:38 -0700 Message-ID: Date: Thu, 11 Jul 2024 11:57:35 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v7 2/4] PCI: qcom-ep: Add support for D-state change notification Content-Language: en-US To: Bjorn Helgaas CC: Manivannan Sadhasivam , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Jonathan Corbet , Lorenzo Pieralisi , Rob Herring , , , , , , , , , , , Manivannan Sadhasivam References: <20240710121118.GA240905@bhelgaas> From: Krishna Chaitanya Chundru In-Reply-To: <20240710121118.GA240905@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mXHbW_6Y4FDFYiXrAqEIVIrBokao0TBO X-Proofpoint-GUID: mXHbW_6Y4FDFYiXrAqEIVIrBokao0TBO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-11_03,2024-07-10_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 adultscore=0 suspectscore=0 phishscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407110043 On 7/10/2024 5:41 PM, Bjorn Helgaas wrote: > On Wed, Jul 10, 2024 at 04:38:15PM +0530, Krishna chaitanya chundru wrote: >> Add support to pass D-state change notification to Endpoint >> function driver. > > Blank line between paragraphs. > Ack. >> Read perst value to determine if the link is in D3Cold/D3hot. > > I assume this reads the state of the PERST# signal driven by the host. > Style it to match the spec usage ("PERST#") to make that connection > clearer. > Ack. > D3cold/D3hot is a device state and doesn't apply to a link. Link > states are L0, L1, L2, L3,etc. Also in cover letter. > Ack. > I don't understand the connection between PERST# state and the device > D state. D3cold is defined to mean main power is absent. Is the > endpoint firmware still running when main power is absent? > Host as part of its d3cold sequence will assert the perst. so we are reading perst to know the link the state. Qcom devices are drawing power from the PCIe, so even when PCIe is in D3cold endpoint firmware can still run. - Krishna Chaitanya. >> Reviewed-by: Manivannan Sadhasivam >> Signed-off-by: Krishna chaitanya chundru >> --- >> drivers/pci/controller/dwc/pcie-qcom-ep.c | 8 +++++++- >> 1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> index 236229f66c80..817fad805c51 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> @@ -648,6 +648,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) >> struct device *dev = pci->dev; >> u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); >> u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); >> + pci_power_t state; >> u32 dstate, val; >> >> writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); >> @@ -671,11 +672,16 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) >> dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & >> DBI_CON_STATUS_POWER_STATE_MASK; >> dev_dbg(dev, "Received D%d state event\n", dstate); >> - if (dstate == 3) { >> + state = dstate; >> + if (dstate == PCI_D3hot) { >> val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); >> val |= PARF_PM_CTRL_REQ_EXIT_L1; >> writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); >> + >> + if (gpiod_get_value(pcie_ep->reset)) >> + state = PCI_D3cold; >> } >> + pci_epc_dstate_notify(pci->ep.epc, state); >> } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { >> dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); >> dw_pcie_ep_linkup(&pci->ep); >> >> -- >> 2.42.0 >>