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Tue, 03 Nov 2026 23:29:42 -0800 (PST) Received: from [192.168.226.1] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c4d0e48b3b7sm40379466b.66.2026.11.03.23.29.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Nov 2026 23:29:41 -0800 (PST) Message-ID: Date: Wed, 4 Nov 2026 08:29:40 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] mailbox: qcom-cpucp: read mbox hardware register using readq() To: Sivansh Gupta Cc: Sibi Sankar , Jassi Brar , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260928052940.688105-1-sivansh.gupta@oss.qualcomm.com> <989045f1-c4c3-4871-92b5-dc9f2a18f801@oss.qualcomm.com> <179189473286.2132802.7434637844183959510.b4-reply@b4> <179377342626.494575.14471451763190105361.b4-reply@b4> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <179377342626.494575.14471451763190105361.b4-reply@b4> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: isP845pX3IevRTzFC6n50ysnsVAA6j7x X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA0MDAyOSBTYWx0ZWRfX/HkuGW+7Smto j7/Tmj+7+Jr0iTz6nv6Hdgwm4ie6ky14Fb544kl0uWzzy6pnpGOZixXaI6xUfxkjLGhJxAuf4IF bFlhn9MTQatlYbZEWBx13qSgkrn/Ed/5vnM8DDPsiHZSgbJUDMcqUZVCmGn9ce/48mIFV6goDm4 v8wpjHj1CWRN7MN9LjQCY44ysKdRoffexpDZbRHUQsClUkEv8yWdtWVU17ciPQ7q51gEoZU3knw QFyVgR0F4djckBiE5/kJ/bpvd4Bh1MsSbAK+p/TJUjiH8BDiUFC3AwxBJWJliGZvOMYuhw9ovDm yhbtuZa/TDvKYlY+FPEV6LR9XOMwv9v9+Pcn+RbJ5K5fvIXIAqehkRjrtnVZr0hWCEhvUGEI891 c7V/ovx0b+SUVikbpdtC94gBMdZLeEhYh4l4vSiB2/w+sG5qgbOPUglcSLfnDxvsMBazeGm62S0 u7jqUG1oOKfPK8gkpJg== X-Proofpoint-ORIG-GUID: isP845pX3IevRTzFC6n50ysnsVAA6j7x X-Authority-Analysis: v=2.4 cv=NMhAaE6g c=1 sm=1 tr=0 ts=6aeadee7 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=bXuMI6HEHXQEcPHf8MwA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA0MDAyOSBTYWx0ZWRfX4DWsOD00KQh6 4UufExNrGDZY3+k7DF9CBhBqJ+Uo+diejTmopnZx7hZyqlTedFcuQt+5AZZiSDM475K07BQQ9vD 8ngiNeCciAnorsyua69vgffxccuUMkk= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-04_01,2026-11-03_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 adultscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611040029 On 11/4/26 7:23 AM, Sivansh Gupta wrote: > On 2026-11-02 16:56 +0100, Konrad Dybcio wrote: >> On 10/13/26 2:32 PM, Sivansh Gupta wrote: >>> On 2026-09-30 11:55 +0200, Konrad Dybcio wrote: >>>> On 9/28/26 7:29 AM, Sivansh Gupta wrote: >>>>> Mailbox hardware registers are 64 bit wide, but the interrupt handler >>>>> currently reads only 32 bits with readl() at offset 0x4 (upper 32 >>>>> bits). This returns an incorrect value, while reading using readq() >>>>> returns the expected value. >>>>> >>>>> Use readq() to access the 64 bit register and pass the expected value >>>>> to the mailbox client. >>>>> >>>>> Fixes: 0e2a9a03106c ("mailbox: Add support for QTI CPUCP mailbox controller") >>>>> Signed-off-by: Sivansh Gupta >>>>> --- >>>>> v3: >>>>> - Removed references to an out of tree driver to focus on the incorrect >>>>> value returned by readl() >>>>> https://lore.kernel.org/all/93ce8588-7500-45da-9b9a-424c202590cf@oss.qualcomm.com/#t >>>>> >>>>> v2: >>>>> - Expanded the commit message to explain why this change is required. >>>>> >>>>> drivers/mailbox/qcom-cpucp-mbox.c | 2 +- >>>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>>>> >>>>> diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c >>>>> index 862e45e8fbd5..0b584d9aad6c 100644 >>>>> --- a/drivers/mailbox/qcom-cpucp-mbox.c >>>>> +++ b/drivers/mailbox/qcom-cpucp-mbox.c >>>>> @@ -61,7 +61,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) >>>>> status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); >>>>> >>>>> for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) { >>>>> - u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); >>>> >>>> This still retains the writel() later on >>> >>> This is intentional, currently the existing mbox client(s) assume 32 bits >>> writes instead of 64 bits, changing to 64 bits here would require all >>> mbox clients to be updated to send 64 bits. >>> Currently there is only 1 upstream client (arm_scmi). >>> >>>>> + u64 val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i)); >>>> >>>> This will alter the indices of the mailbox channels, but it's ""fine"" >>>> because it's always zero for the existing platforms.. >>>> >>>> Konrad >>> >>> I am unsure what you mean here. The channel registers are spaced 8 bytes >>> apart. In the old code, we used to read each channel's upper 32 bits >>> (channel base + 4 bytes), in the new code we will be reading the entire >>> 8 bytes. >>> If this is not what you meant, please let me know! >> >> You're right, please remove the leftover define > > Hey, APSS_CPUCP_MBOX_CMD_OFF is intentionally used in > qcom_cpucp_mbox_send_data as it is still using writel instead of writeq, > as we discussed. > > Also, I have since learned that this patch has already been picked up! > > Cheers, Sivansh Ok, all is well that ends well Konrad