From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752476AbdBFBkp (ORCPT ); Sun, 5 Feb 2017 20:40:45 -0500 Received: from regular1.263xmail.com ([211.150.99.139]:52996 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751532AbdBFBkn (ORCPT ); Sun, 5 Feb 2017 20:40:43 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: frank.wang@rock-chips.com X-FST-TO: frank.wang@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: frank.wang@rock-chips.com X-UNIQUE-TAG: <557a56775b835bd05d745481c225758f> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [RESEND PATCH 0/1] add multiple clock handling for dwc2 driver To: Heiko Stuebner References: <1486263061-10681-1-git-send-email-frank.wang@rock-chips.com> <3508420.z4eX5F6ytJ@phil> Cc: johnyoun@synopsys.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-rockchip@lists.infradead.org, huangtao@rock-chips.com, kever.yang@rock-chips.com, william.wu@rock-chips.com, elaine.zhang@rock-chips.com, frank.wang@rock-chips.com From: Frank Wang Message-ID: Date: Mon, 6 Feb 2017 09:40:35 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <3508420.z4eX5F6ytJ@phil> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Heiko, On 2017/2/5 17:41, Heiko Stuebner wrote: > Hi Frank, > > Am Sonntag, 5. Februar 2017, 10:51:00 CET schrieb Frank Wang: >> The original posting on Jan 19th have not received any responses, so I >> resend them. >> >> The Current default dwc2 just handle one clock named otg, however, it may >> have two or more clock need to manage for some new SoCs(such as RK3328), so >> this adds change clk to clk's array of dwc2_hsotg to handle more clocks >> operation. > can you please give a bit more detail on the specific layout. > > I guess you're talking about hclk_otg_pmu, right? What component does it > supply, because I didn't find anything in the partial TRM in the PMU section > relating to the "otg". Yes, it is hclk_otg_pmu. The rock-chip hclk_otg_pmu is an input clock for dwc2 PMU module which named pmu_hclk in chapter 2.4 of dwc otg databook v3.10. Please refer to the following simple clock tree from CRU part of rk3328 TRM. _ _ _ ... | |- - -> G19_8 - - - hclk_otg - - - - - - -> hclk_peri_pre - - ->| |- - -> G19_9 - - - hclk_otg_pmu - - -> |_ _ _ ... BR. Frank > This meant to make sure, you're actually controlling some part of the dwc2 > with that second/third/... clock and not some separate component. > > > Heiko > > >