Re: [PATCH v3 02/13] ASoC: amd: acp: add ACP7.B/7.F SoundWire DAI link support

["Mukunda,Vijendar" <vijendar.mukunda@amd.com>]

On 26/10/26 02:41, Pierre-Louis Bossart wrote:
> It'd be useful to comment/explain why this routine only relies on a
> subset of IDS...
On ACP7x, each SoundWire data port has a dedicated DMA channel mapped
in hardware. This function selects only the ports required by the
currently supported ACP7x machine topologies:

  AUDIO0_TX (0)  - headset/jack playback
  AUDIO4_TX (4)  - amplifier/speaker playback
  AUDIO0_RX (11) - headset/jack capture
  AUDIO4_RX (15) - amplifier/speaker capture (feedback)
  AUDIO5_RX (16) - DMIC capture

The remaining port IDs are defined for completeness to represent the
hardware data port layout, but are not used by the currently supported
machine topologies.

The ID numbering differs from ACP70 due to the hardware differences
between ACP70 and ACP7x. ACP7x uses a flat ID space, with TX ports
numbered 0-10 and RX ports numbered 11-21.

Will add comments above the define block and the function to clarify
this in the next version.

>
>> +int get_acp7x_cpu_pin_id(u32 sdw_link_id, int be_id, int *cpu_pin_id, struct device *dev)
>> +{
>> +	switch (sdw_link_id) {
>> +	case AMD_SDW0:
>> +	case AMD_SDW1:
>> +	case AMD_SDW2:
>> +	case AMD_SDW3:
>> +		switch (be_id) {
>> +		case SOC_SDW_JACK_OUT_DAI_ID:
>> +			*cpu_pin_id = ACP7X_SW_AUDIO0_TX;
>> +			break;
>> +		case SOC_SDW_JACK_IN_DAI_ID:
>> +			*cpu_pin_id = ACP7X_SW_AUDIO0_RX;
>> +			break;
>> +		case SOC_SDW_AMP_OUT_DAI_ID:
>> +			*cpu_pin_id = ACP7X_SW_AUDIO4_TX;
>> +			break;
>> +		case SOC_SDW_AMP_IN_DAI_ID:
>> +			*cpu_pin_id = ACP7X_SW_AUDIO4_RX;
>> +			break;
>> +		case SOC_SDW_DMIC_DAI_ID:
>> +			*cpu_pin_id = ACP7X_SW_AUDIO5_RX;
>> +			break;
>> +		default:
>> +			dev_err(dev, "Invalid be id:%d\n", be_id);
>> +			return -EINVAL;
>> +		}
>> +		break;
>> +	default:
>> +		return -EINVAL;
>> +	}
>> +	dev_dbg(dev, "sdw_link_id:%d, be_id:%d, cpu_pin_id:%d\n", sdw_link_id, be_id, *cpu_pin_id);
>> +	return 0;
>> +}
> ... defined here - I marked the NOT USED ones.
Please refer above comment explanation.
>
>> +/* ACP7.B/7.F SoundWire CPU pin IDs */
>> +#define ACP7X_SW_AUDIO0_TX	0
>> +#define ACP7X_SW_AUDIO1_TX	1 << NOT USED
>> +#define ACP7X_SW_AUDIO2_TX	2 << NOT USED
>> +#define ACP7X_SW_AUDIO3_TX	3 << NOT USED
>> +#define ACP7X_SW_AUDIO4_TX	4 
>> +#define ACP7X_SW_AUDIO5_TX	5 << NOT USED
>> +#define ACP7X_SW_AUDIO6_TX	6 << NOT USED
>> +#define ACP7X_SW_AUDIO7_TX	7 << NOT USED
>> +#define ACP7X_SW_AUDIO8_TX	8 << NOT USED
>> +#define ACP7X_SW_AUDIO9_TX	9 << NOT USED
>> +#define ACP7X_SW_AUDIO10_TX	10 << NOT USED
>> +
>> +#define ACP7X_SW_AUDIO0_RX	11
>> +#define ACP7X_SW_AUDIO1_RX	12 << NOT USED
>> +#define ACP7X_SW_AUDIO2_RX	13 << NOT USED
>> +#define ACP7X_SW_AUDIO3_RX	14 << NOT USED
>> +#define ACP7X_SW_AUDIO4_RX	15
>> +#define ACP7X_SW_AUDIO5_RX	16
>> +#define ACP7X_SW_AUDIO6_RX	17 << NOT USED
>> +#define ACP7X_SW_AUDIO7_RX	18 << NOT USED
>> +#define ACP7X_SW_AUDIO8_RX	19 << NOT USED
> The IDs are different from what was used for ACP70

ACP7x hardware exposes 11 TX and 11 RX data ports, mapped to 8 TX and
8 RX DMA channels. The CPU pin IDs use linear numbering, with TX ports
numbered 0-10 and RX ports numbered 11-21.

The ID mapping differs from ACP70 due to the hardware differences
between ACP70 and ACP7x. All port IDs are defined here to represent the
ACP7x hardware data port layout.