From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 735EACE79AC for ; Wed, 20 Sep 2023 07:30:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233739AbjITHaj (ORCPT ); Wed, 20 Sep 2023 03:30:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233534AbjITHah (ORCPT ); Wed, 20 Sep 2023 03:30:37 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF7E4CE for ; Wed, 20 Sep 2023 00:30:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695195024; x=1726731024; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=+f/SlsffWN3dCi/VtuiZU8f+moZRzVKgS6ofi5xty3Q=; b=hBbw6qMK/UXmmZzxTnhjl/vqGLUsY+pcUpfbQYut01luIz4VfUCyLUxt i5LgprlhbP77QeYJrgN+yLKii412wj9wRg8eebBckNvalCgJcQ7s1s/9m o15j2dXae5RtNcLiAyBsRdXqGu28WvDuanZzAg+pz9TiHIKOJj7u2xLMF 708XqpCct1VHdnsyJ/877l3x6GNd5fuH0rM4kpgAHvTAn05xTw2chWkTM fuUPdzHIWE/Wt7ct148j/rk0+TEBxnJ0naBpUGoO6S+i31tHAJD5ZRpvl YInpkCPmC4HYlh+ZcO8/+oqoNYF3WR2PSSnbLgl3u0nssCJKyN9Wrrg43 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="383995573" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="383995573" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 00:30:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="870266763" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="870266763" Received: from lingshan-mobl.ccr.corp.intel.com (HELO [10.93.14.5]) ([10.93.14.5]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 00:30:17 -0700 Message-ID: Date: Wed, 20 Sep 2023 15:30:14 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.15.1 Subject: Re: [virtio-dev] Re: [virtio-comment] Re: [VIRTIO PCI PATCH v5 1/1] transport-pci: Add freeze_mode to virtio_pci_common_cfg Content-Language: en-US To: "Chen, Jiqian" , Parav Pandit , "Michael S. Tsirkin" Cc: Gerd Hoffmann , Jason Wang , Xuan Zhuo , David Airlie , Gurchetan Singh , Chia-I Wu , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Robert Beckett , Mikhail Golubev-Ciuchea , "virtio-comment@lists.oasis-open.org" , "virtio-dev@lists.oasis-open.org" , "qemu-devel@nongnu.org" , "linux-kernel@vger.kernel.org" , Stefano Stabellini , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= , "Deucher, Alexander" , "Koenig, Christian" , "Hildebrand, Stewart" , Xenia Ragiadakou , "Huang, Honglei1" , "Zhang, Julia" , "Huang, Ray" References: <20230919114242.2283646-1-Jiqian.Chen@amd.com> <20230919114242.2283646-2-Jiqian.Chen@amd.com> <20230919082802-mutt-send-email-mst@kernel.org> <701bb67c-c52d-4eb3-a6ed-f73bd5d0ff33@intel.com> From: "Zhu, Lingshan" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/20/2023 3:24 PM, Chen, Jiqian wrote: > Hi Lingshan, > It seems you reply to the wrong email thread. They are not related to my patch. These reply to Parva's comments. @Parva, if you want to discuss more about live migration, please reply in my thread, lets don't flood here. > > On 2023/9/20 15:06, Zhu, Lingshan wrote: >> >> On 9/20/2023 2:58 PM, Parav Pandit wrote: >>>> From: Chen, Jiqian >>>> Sent: Wednesday, September 20, 2023 12:03 PM >>>> If driver write 0 to reset device, can the SUSPEND bit be cleared? >>> It must as reset operation, resets everything else and so the suspend too. >>> >>>> (pci_pm_resume->virtio_pci_restore->virtio_device_restore- >>>>> virtio_reset_device) >>>> If SUSPEND is cleared, then during the reset process in Qemu, I can't judge if >>>> the reset request is from guest restore process or not, and then I can't change >>>> the reset behavior. >>> Reset should not be influenced by suspend. >>> Suspend should do the work of suspend and reset to do the reset. >>> >>> The problem to overcome in [1] is, resume operation needs to be synchronous as it involves large part of context to resume back, and hence just asynchronously setting DRIVER_OK is not enough. >>> The sw must verify back that device has resumed the operation and ready to answer requests. >> this is not live migration, all device status and other information still stay in the device, no need to "resume" context, just resume running. >> >> Like resume from a failed LM. >>> This is slightly different flow than setting the DRIVER_OK for the first time device initialization sequence as it does not involve large restoration. >>> >>> So, to merge two ideas, instead of doing DRIVER_OK to resume, the driver should clear the SUSPEND bit and verify that it is out of SUSPEND. >>> >>> Because driver is still in _OK_ driving the device flipping the SUSPEND bit. >> Please read the spec, it says: >> The driver MUST NOT clear a device status bit >> >>