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Tue, 23 Dec 2025 02:49:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IH1v/1HacvwG7DWXzwiLrvcU2Zusz8BK/bUppipGd3g3H//7IAWFp+IVDMaldG9feohRs6Z6A== X-Received: by 2002:a05:6a00:6b93:20b0:7b8:acdd:23c3 with SMTP id d2e1a72fcca58-7fe0c0fbefbmr11463420b3a.11.1766486968718; Tue, 23 Dec 2025 02:49:28 -0800 (PST) Received: from [10.217.217.147] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7e88cd71sm13327808b3a.64.2025.12.23.02.49.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Dec 2025 02:49:28 -0800 (PST) Message-ID: Date: Tue, 23 Dec 2025 16:19:20 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 07/11] dt-bindings: clock: qcom: document the Kaanapali GPU Clock Controller To: Krzysztof Kozlowski , Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Vladimir Zapolskiy , Konrad Dybcio , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Jingyi Wang , Bryan O'Donoghue References: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> <20251125-kaanapali-mmcc-v2-v2-7-fb44e78f300b@oss.qualcomm.com> <20251126-elated-stoic-scorpion-25b630@kuoka> <503f445e-0d12-407d-bc77-f48ad335639b@oss.qualcomm.com> <3e8128f4-3cba-4c13-a846-e5f1638a1e0f@kernel.org> <701a7b2f-848a-4cc0-8924-ec72155d93a7@oss.qualcomm.com> <65e5459b-7509-47db-9089-6efecead3f44@kernel.org> Content-Language: en-US From: Taniya Das In-Reply-To: <65e5459b-7509-47db-9089-6efecead3f44@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=ELgLElZC c=1 sm=1 tr=0 ts=694a73ba cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=PurT2Iiaq-uxMnD6zWEA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIzMDA4NiBTYWx0ZWRfX6NKDPXopjG4f SHxtFFYqVh7LBZjVFm7FMBhsW3gvnOP12mLQXAjZWMyZ/5vXbBsvpcdipyCtO7J4tQnSoZROreK qimUzNMUx87me6jqZhQvKpYufSuBJHll4dYBN/0yQIeqBgNqvCz6k1wi5yJJC9bB3klk/O7iA2z d7gMVCf5H/ZVq4m5Uz2CV0BhIt9NKjalFcn1gWa1jeHfxPm+U61q9pK3L6quNwyH6ooFojjRgKj 1wYb1j8oh7oywjiby51HIcitZRpcpGS1ytxrXCRpwOPDh1al/cgvm2GuCL564sQBdWKqv5nuuYL ASuNmnYVDJHeJaa73TOWbtgj+D2mkQuh7Nw4kwmiPkIvY6XAMJU+0DsBVJOrpifeGgowEKrQ8wO AEQHwgWXz8uDuD+zMpWanIrtpDqFKmTDx2D/pA87OpL56PfghHHBU0aEqvqRsMMxAB7UzXPew4v z8Pbdysi8P9VM8rlnEg== X-Proofpoint-GUID: AI0PmnWuP_VvQxxzMtDs3h6n3HhHScm5 X-Proofpoint-ORIG-GUID: AI0PmnWuP_VvQxxzMtDs3h6n3HhHScm5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-23_03,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 adultscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512230086 On 12/19/2025 8:15 PM, Krzysztof Kozlowski wrote: > On 19/12/2025 14:02, Konrad Dybcio wrote: >> On 12/17/25 2:54 PM, Krzysztof Kozlowski wrote: >>> On 17/12/2025 14:21, Konrad Dybcio wrote: >>>> On 12/17/25 11:09 AM, Krzysztof Kozlowski wrote: >>>>> On 17/12/2025 10:32, Taniya Das wrote: >>>>>>>> >>>>>>>> We would like to leverage the existing common clock driver(GDSC) code to >>>>>>> >>>>>>> Fix the driver code if it cannot handle other cells. Your drivers do not >>>>>>> matter for choices made in bindings. >>>>>>> >>>>>> >>>>>> As it is still a clock controller from hardware design and in SW I will >>>>>> be map the entire hardware region and this way this clock controller >>>>>> will also be aligned to the existing clock controllers and keep the >>>>>> #power-domain-cells = <1> as other CCs. >>>>> >>>>> I don't see how this resolves my comment. >>>> >>>> Spanning the entire 0x6000-long block will remove your worry about this >>>> description only being 2-register-wide >>> >>> But that was not the comment here. Taniya replied under comment about >>> cells. We are not discussing here some other things... >> >> Right, you omitted the part where I answered your comment from the >> context, so I'll re-add it: >> >> """ >> This block provides more than one GDSC - although again, not all of them >> need/should be accessed by Linux. I suppose just enumerating the "extra" >> ones in bindings will be a good enough compromise? >> """ >> >> TLDR: cells=1 makes sense as per usual > > Either list them in headers or at least explain that in the binding. I will take care to list them and explain them as well. -- Thanks, Taniya Das