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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b105864375sm9085247a91.4.2026.11.08.18.58.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 08 Nov 2026 18:58:52 -0800 (PST) Message-ID: Date: Mon, 9 Nov 2026 10:58:48 +0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/6] arm-mpam: Add basic device tree support for resctrl To: Rob Herring , Ping Li Cc: james.morse@arm.com, ben.horgan@arm.com, sdonthineni@nvidia.com, andre.przywara@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261028-mpam-resctrl-dt-knp-support-v4-0-bdda1e445cba@oss.qualcomm.com> <20261104081302.304667-1-leeonion.muyu@gmail.com> <9d370f12-9e4c-4b80-9d28-ff8085ce3aee@oss.qualcomm.com> <20261105055347.947416-1-leeonion.muyu@gmail.com> <20261106150822.GA3193214-robh@kernel.org> Content-Language: en-US From: Yin Li In-Reply-To: <20261106150822.GA3193214-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 1L3TtaSupd7faxOWRG74obR2O1iwP6JS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA5MDAxMSBTYWx0ZWRfXygdpaMcm8bx3 aJqUE/h55ZC4sR6wBKmpBynE3PP+f4le+LtDu/NaAQoEtFMhaM9EFqO334lhmB+PhQzBRdyxnvw UQGYd4dYgaxbTNmoLTdjSdhlbvUw93rwqGk+bVUI52Og7IN7cYYqZ5quM+SwQz1htm3SNUfdsSD E4MzP9U5qLccH3iRrai7fmxZDIwJ1j3EmF1tGuNuPPp/UCGo8/MgQbAF4bq8WdQHhfAaKL+FW4H oocybW2J8bgJe0GnE4nRNGIKJJB3zYQEf7W90uxxdK0DGGEoWzYsWWCKuHTaR/uMoBeaKRu8lk5 UGmjcv2RYn3hBJx8MMEDRSgx4E0AklhFxzHrou7wpEg4inHtVI1fZK+sJvH/Zr3JdHXdH+93HG8 wNudJKuL5Opzw52G1FOzgMXAIO4p+rsR0Wywk3Sb6CpOj8C66LKmbzZIm2stEF/AoBBwtmVlazG 0oVV9driXgjQKMuTjhA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA5MDAxMSBTYWx0ZWRfX28ft+7UosV/s 7rJ2dJY1aHX5iWPlatFhM9/Zp88ngeEiJhtQuYDO//JNGLxqi9iztBLK18HRU6mA+pl24IzxbN0 bhlKzuJChK87B8sgH1+cryXsaSCaQU4= X-Authority-Analysis: v=2.4 cv=TeIDJhQh c=1 sm=1 tr=0 ts=6af136ee cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=aeo0eiRZ57vjQv3oqWoA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: 1L3TtaSupd7faxOWRG74obR2O1iwP6JS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-09_01,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 phishscore=0 bulkscore=0 adultscore=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611090011 On 11/6/2026 11:08 PM, Rob Herring wrote: > On Thu, Nov 05, 2026 at 01:53:47PM +0800, Ping Li wrote: >> Hi Yin, >> >> Sure. Our memory controller MSC is described as a top-level node. >> The MPAM register window is mapped independently in the SoC (the >> component sits on the DDR egress path rather than being a sub-block >> of a memory-controller DT node), so the node is a direct child of >> the root: >> >> ddr_msc: msc@2238000 { >> compatible = ",-ddr-qos", >> "arm,mpam-memory-controller-msc", >> "arm,mpam-msc"; >> reg = <0x0 0x02238000 0x0 0x1000>; >> arm,not-ready-us = <10>; >> }; >> >> The first compatible in the list is for our platform glue; I have >> replaced it with a placeholder here since it is not relevant to the >> binding discussion. >> >> Notes on the properties, in case they matter for the binding: >> >> - reg: the MPAM register window. Only a subset of the architectural >> register space is implemented, so the size is the truncated window. >> - single RIS: the component reports HAS_RIS=0, so there are no >> ris@N child nodes. >> - no interrupts: the component has no MPAM ESR block, so there is >> no interrupts property. >> - arm,not-ready-us: 10. >> >> The verified probe path: the node matches via "arm,mpam-msc", and >> patch 6/8 in v3 classifies it as MPAM_CLASS_MEMORY and treats it as >> accessible from all CPUs, which is exactly the behavior we need. >> >> One question in return: with the node being a direct child of the >> root rather than a child of a memory-controller node, is that a >> form the binding should cover? If the binding expects the MSC to >> always be a sub-node of a memory controller, we would need the >> top-level form to be allowed as well. > > This would be why we're not upstreaming the binding without users. We > need actual h/w to validate the binding works. > Hi Ping, Rob, Ping, thank you for the detailed description and for confirming this on hardware. To answer your question: the top-level form should be supported. Unlike cache MSCs, where both class_id and component_id are derived from the parent cache node, memory controller MSCs derive both from the MSC node itself via of_node_to_nid(). There is no requirement for the MSC to be a sub-node of a memory-controller node. Rob, with Ping's hardware-validated use case covering the top-level form, we would like to restore memory controller MSC support in v5. We will use Ping's DT as a reference for the binding example. Ping, a Tested-by from you would be very welcome once v5 is posted. Thanks, Yin > Rob -- Thx and BRs, Yin