From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79FE41A08AF for ; Tue, 7 Apr 2026 02:35:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775529358; cv=none; b=lZEc8dZgX+wlovs7jZ6yZF1K55OMKOgRvCqAL56lb7hQ2P9Cj6nnPjyLlHEWAzxB6CTJ1GmqKhxXcNA+ZBuKh5VCHXPB2S8li6CO6NGty82Yr2JAts9CSTdF5uY6MXm/9a2Zw9kHrBGzMgBInVltwCsq6LYkmqgHi9JzEv2PofA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775529358; c=relaxed/simple; bh=g30wszMAxyXajPK6C5fviVRDfBK78m+7vidE9j+5ZnA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Ii9BFUcdb066Lx+SLUEcM7d54sANpA2hnW2LZOlfQf+1RWE/bxhwsS3epMEH7BG2pnuyh88+5xDrPxhFF4zBeUp0wFA46bg/ogAHhTN3+ded5jZab1qVt8MFK6pS9tzzXasBCdNmOexIXwSRcscLQMNSm2NCISb8XZjwrW6oy1U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=a7VnEzaS; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=NGys3Q/h; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="a7VnEzaS"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="NGys3Q/h" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 636LPjoh3815649 for ; Tue, 7 Apr 2026 02:35:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pKWZGWsm+uinU5enYlneg7o88Oa9y0lewOd8+OxYdEo=; b=a7VnEzaSz691Ni60 jHHQs8DzeX3CnTDVWSMcEOhnPdsUc/yi2a3iUwS2TK3anYUaCPHVbRLUU7O0sJ2r eyo2Xk8ivIgtl09y/ife7H2Ny/61ta0uZahK8bNEphAYEdXVY5/wyUQaXGLcRqGF F7bo5MwoROvwPTnDX0siGeS3wR3t661Z4Pjipvcb6PRL4zLYq4u26xcAscEwB7xO s3bjYGlkl8XG6hzz0dIkBTwK2VgzwfPXXBOVhL7C0dtjiy0J8v5iHB5RCc15HLyC bpRYHsdcERjKu3NHbCFegRXnaJb0ulTF28l3d1DxJfUGGCsG2zpvws45f/5eqlou UXU9sQ== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dcmr4rnwq-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 07 Apr 2026 02:35:56 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2a90510a6d1so34236445ad.0 for ; Mon, 06 Apr 2026 19:35:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1775529355; x=1776134155; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=pKWZGWsm+uinU5enYlneg7o88Oa9y0lewOd8+OxYdEo=; b=NGys3Q/hkGGDsoUQJ8Pwfw5r06aYrn2D8zq+H/n/9GaksCvSDwiTFgUqPHqifMQrYO GvaPZTTIs0nlXkUIdcRa8MbaazxPbLyxtYpJD6IMCHzVdrxJlRUHda9IJRdkb5DsCUeL TJE4pxgzgITtVOdUyY/ADG5ptN7s61DjKSzA1tm6zStWBZA3iUM8HxmMHxVELU6MXZfU a+qqta5JkgtTlqroKqnZIdClCyPR2OWtxEs49OggGElZsJiDyXgOsa6mh/YZNCKjRQAp UxL/C/QI+/zasUvkyz51BLEU9b53xf3sJOdD73JP2wzbwuoUIQrqGlJ+MGH9vUQaiZfp 5W4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775529355; x=1776134155; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=pKWZGWsm+uinU5enYlneg7o88Oa9y0lewOd8+OxYdEo=; b=UEzTW/nbrDdEveeCexMCWA/+C1T8hlAqxKpFquutJk9nwaGsanb7z6dynu1eq6Wlbk HOHSuNv1aDYjwI1qnMKlyaGCWRgMG6aJQlDj0Hsq6+VkbixJ/ijJrVbaEojO8VCc9tCn 0992ZaVd04ulPoH5VeaVfmzBgXuoX351Pa5i6/byPIb/NZLabS4eBX1/KTvI6rPYot04 ofjIOiNbsj0PrYfVRfPyup2OMVodcOfb9OsTVofBPI0zNHmbipRdBI9C3K3BpSEYIPmH zYtYe6tTvtL7yUB9micos4A5eoG57S+LuRQzmR4oqSG4CuxVBcsYJzGAl9PxYVcDtDav CX5w== X-Forwarded-Encrypted: i=1; AJvYcCXXU76OmpmJgwHhqWrpSKUkObSXndzAk6GZffT2Q03v+uFZFpJOjfXqBc+8MVqprLvGzteAwbSRV+KqFik=@vger.kernel.org X-Gm-Message-State: AOJu0YxJ6umWAybGylTcPT6zLQVO83TVi6al/g9t0m1rB5AvgioLKhOT lwaW7woDspda3nS+yPFzmNn6s4MgJPR1ok/dO6QiTb03L7h+/nBjB3Nvk449UsuyHcsXuF9e4Uc tW78IdKJGyOZjk2g7Peuym2s5eytQeGYhi3nrtzzwvmmGDX3iPSs/ZnotbhNMMFxCpjybZ5LwDG 0= X-Gm-Gg: AeBDietkzOn3fUcJH/FwIlihy7eNsyzrzXEP/8cSMTa5Vb+UdGRUQ9hKg4SKxh5myDG IPJvMz7jaRdK9WWfniz1LBuJqkzOCanBEr83KWJ5kZTciDAUtdNsvWjp3/oGCVxcMGbX7dG45fU 2K/nclv0+QAUTXroJimi78J/4GIvDx8MtUd+QFGFfEO4SePfuiWYOR2ygLlMF+gKbPC6QZwN7P/ ezvMFbXwYJrRoBKJxazH/J+lXQgUhpSUmY2SVgbV07ipG9mdwYMaWvNVyKpQwBFCIQrlRZ73SWi jvzAdmjgK7Gav2CgUNDgGLT3VNmD8CHuKi2DSQZmJrzTCvYD79lNl7mG3lNI7gOcgeaonFJLfd6 TNw61K7keH/DiksQZPYcgYqQKS9AoAHBUF6uMgdr1glFvGiOs5pSAx0fX8QXQInbMKTzH6q1tih PiRO+K+BvcaT/MpYbS0w== X-Received: by 2002:a17:903:388b:b0:2ae:5ab4:f4c0 with SMTP id d9443c01a7336-2b28205a9d8mr144906005ad.13.1775529355063; Mon, 06 Apr 2026 19:35:55 -0700 (PDT) X-Received: by 2002:a17:903:388b:b0:2ae:5ab4:f4c0 with SMTP id d9443c01a7336-2b28205a9d8mr144905685ad.13.1775529354518; Mon, 06 Apr 2026 19:35:54 -0700 (PDT) Received: from [10.133.33.129] (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b27497af19sm149001615ad.50.2026.04.06.19.35.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Apr 2026 19:35:54 -0700 (PDT) Message-ID: Date: Tue, 7 Apr 2026 10:35:49 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 34/38] drm/msm: initialize DRM MST encoders for DP controllers To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar References: <20250825-msm-dp-mst-v3-0-01faacfcdedd@oss.qualcomm.com> <20250825-msm-dp-mst-v3-34-01faacfcdedd@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=dO6WXuZb c=1 sm=1 tr=0 ts=69d46d8c cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=Bl6qu2857310sCFhzq4A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: t1Ux3Xyo3xW3vxPjXjOoMmkKxiLbuBbF X-Proofpoint-ORIG-GUID: t1Ux3Xyo3xW3vxPjXjOoMmkKxiLbuBbF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA3MDAyMyBTYWx0ZWRfXy1gjwCoxAnzf CfpRsDs7o/1Jc9TW+V7E9e5SeUKm/Tm1IWSQId40xwOJHbkWLT2kcBe9kPfIg80H0n45RPwlheT JNjzWzQw9Cfs7YirHkpUJ8YUJMCWBWlbCAlNAYY2U6bfaJuTOev5iAna90nnXuEnYYsdxNvAppo UUXw5yEJTMhU6DDCpYAlJGvhdkZJM+F466jUf8GjjFOAdsyR5eEqFXlBkcbNg7C9M7XbkbEzpnN /ZBJk7bRlmJJlW+EuRZfXZ0CQhtLQ2sytNv9S+8256HAZWcCFv5EsYw/wSHdsvb3Fc6uSr+roZj Z9Cw4rBZTkNBi57pbMEAVrpPIpzSYTdoWE4/W+WpuS9fxdxjM2VNDc9odedeFX6lA6xd/1YOPrh JUbpICSn9fB0D7DN9jBWBbkBmb5z/cJktqW7kwtjKYiBsaPAGcS2tt6OzmegM6ixI1euwsMgoET 6WxQaKtb9SPObbIiW7w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-07_01,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604070023 On 8/27/2025 2:55 AM, Dmitry Baryshkov wrote: > On Mon, Aug 25, 2025 at 10:16:20PM +0800, Yongxing Mou wrote: >> From: Abhinav Kumar >> >> Initialize a DPMST encoder for each MST capable DP controller >> and the number of encoders it supports depends on the number >> of streams it supports. >> >> Signed-off-by: Abhinav Kumar >> Signed-off-by: Yongxing Mou >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++ >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 23 ++++++++++++++++++++++- >> drivers/gpu/drm/msm/dp/dp_mst_drm.h | 2 -- >> drivers/gpu/drm/msm/msm_drv.h | 13 +++++++++++++ >> 4 files changed, 37 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h >> index ca1ca2e51d7ead0eb34b27f3168e6bb06a71a11a..2eb4c39b111c1d8622e09e78ffafef017e28bbf6 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h >> @@ -28,6 +28,7 @@ >> * @h_tile_instance: Controller instance used per tile. Number of elements is >> * based on num_of_h_tiles >> * @is_cmd_mode Boolean to indicate if the CMD mode is requested >> + * @stream_id stream id for which the interface needs to be acquired >> * @vsync_source: Source of the TE signal for DSI CMD devices >> */ >> struct msm_display_info { >> @@ -35,6 +36,7 @@ struct msm_display_info { >> uint32_t num_of_h_tiles; >> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; >> bool is_cmd_mode; >> + int stream_id; >> enum dpu_vsync_source vsync_source; >> }; >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> index 12dcb32b472497f9e59619db4e810abfbf610c7c..0b9d9207f4f69e0d0725ff265c624828b5816a8b 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> @@ -653,7 +653,8 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, >> struct msm_display_info info; >> bool yuv_supported; >> int rc; >> - int i; >> + int i, stream_id; >> + int stream_cnt; >> >> for (i = 0; i < ARRAY_SIZE(priv->kms->dp); i++) { >> if (!priv->kms->dp[i]) >> @@ -676,6 +677,26 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, >> DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); >> return rc; >> } >> + >> + stream_cnt = msm_dp_get_mst_max_stream(priv->kms->dp[i]); >> + >> + if (stream_cnt > 1) { >> + for (stream_id = 0; stream_id < stream_cnt; stream_id++) { >> + info.stream_id = stream_id; >> + encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); >> + if (IS_ERR(encoder)) { >> + DPU_ERROR("encoder init failed for dp mst display\n"); >> + return PTR_ERR(encoder); >> + } >> + >> + rc = msm_dp_mst_drm_bridge_init(priv->kms->dp[i], encoder); > > This is an implementation detail. We should be asking to init MST, which > might or might not be a bridge. > Got it. How about renaming it to msm_dp_mst_attach_encoder? >> + if (rc) { >> + DPU_ERROR("dp mst bridge %d init failed, %d\n", > > DP, MST, no 'bridge'. > Got it. Thanks. >> + stream_id, rc); >> + continue; >> + } >> + } >> + } >> } >> >> return 0; >> diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/dp_mst_drm.h >> index 8fe6cbbe741da4abb232256b3a15ba6b16ca4f3e..d73e3f908439094532e88945ed4d41ed092051c9 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.h >> +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h >> @@ -82,8 +82,6 @@ struct msm_dp_mst_connector { >> struct msm_dp_panel *dp_panel; >> }; >> > >> -int msm_dp_mst_drm_bridge_init(struct msm_dp *dp, struct drm_encoder *encoder); >> - > > Squash this and the next chunks to the corresponding patches. > Will rework it. >> int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm_dp_aux *drm_aux); >> >> void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display); >> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h >> index 985db9febd98e35dfed51d39dac1a522abe5a351..3e64ec7b7dbe1d1107e85def9aa80277131f40bf 100644 >> --- a/drivers/gpu/drm/msm/msm_drv.h >> +++ b/drivers/gpu/drm/msm/msm_drv.h >> @@ -363,6 +363,9 @@ bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, >> const struct drm_display_mode *mode); >> bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); >> >> +int msm_dp_get_mst_max_stream(struct msm_dp *dp_display); >> +int msm_dp_mst_drm_bridge_init(struct msm_dp *dp_display, struct drm_encoder *encoder); >> + >> #else >> static inline int __init msm_dp_register(void) >> { >> @@ -379,6 +382,16 @@ static inline int msm_dp_modeset_init(struct msm_dp *dp_display, >> return -EINVAL; >> } >> >> +static inline int msm_dp_get_mst_max_stream(struct msm_dp *dp_display) >> +{ >> + return -EINVAL; >> +} >> + >> +static inline int msm_dp_mst_drm_bridge_init(struct msm_dp *dp_display, struct drm_encoder *encoder) >> +{ >> + return -EINVAL; >> +} >> + >> static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) >> { >> } >> >> -- >> 2.34.1 >> >