From: Ryan Brue <ryanbrue.dev@gmail.com>
To: Chen-Yu Tsai <wenst@chromium.org>,
Daniel Lezcano <daniel.lezcano@kernel.org>,
Thomas Gleixner <tglx@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Cc: Luca Leonardo Scorcia <l.scorcia@gmail.com>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clocksource/drivers/timer-mediatek: Don't override the arch timer sched_clock
Date: Tue, 10 Nov 2026 20:24:11 -0600 [thread overview]
Message-ID: <a6a47813-97e7-4d22-b8e6-7dfab8ae79ce@gmail.com> (raw)
In-Reply-To: <20261109120757.847266-1-wenst@chromium.org>
Hi Chen-Yu,
On 11/9/26 6:07 AM, Chen-Yu Tsai wrote:
> Before the conversion, both drivers used TIMER_OF_DECLARE and
> timer-mediatek.o is linked before arm_arch_timer.o, so the arch timer
> registered last and won.
On MT8173 the GPT already replaced the arch timer as sched_clock before
7a097aba7255. Every boot log I have from 7.3 on the Fire HD 10 shows the
same swap, for example on 7.3.0-rc5:
[ 0.000000] arch_timer: cp15 timer running at 13.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff
max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps
every 4398046511101ns
[ 0.000366] clocksource: timer: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 147020034397 ns
[ 0.000378] sched_clock: 32 bits at 13MHz, resolution 76ns, wraps
every 165191050201ns
and on 7.3.0-rc6:
[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps
every 4398046511101ns
[ 0.000192] clocksource: timer: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 147020034397 ns
[ 0.000201] sched_clock: 32 bits at 13MHz, resolution 76ns, wraps
every 165191050201ns
Neither kernel had changes to drivers/clocksource or kernel/time iirc.
I think the reason is that timer_probe() walks the device tree nodes in
order and matches each one against __timer_of_table, so link order only
decides which entry a node matches, not which timer initializes first.
In mt8173.dtsi the arm,armv8-timer node comes before soc/timer@10008000,
so the GPT registered second then too, and with the same rate it
replaced the arch timer.
So what the conversion changed is when the swap happens, late enough to
trigger the splat, rather than whether it happens.
The patch still LGTM, and it gives MT8173 the 56-bit arch counter back.
It's just the history paragraph that I wanted to give my anecdote for.
On the Fire HD 10 (2017), v7.4-rc2 with this patch prints only
"sched_clock: 56 bits at 13MHz", where the rc1 boot before it switched
to the GPT's 32 bits. Boot, suspend/resume, and cpufreq are fine.
Tested-by: Ryan Brue <ryanbrue.dev@gmail.com> # on Amazon Fire HD 10
(MT8173)
Thanks!
Ryan Brue
prev parent reply other threads:[~2026-11-11 2:24 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-09 12:07 Chen-Yu Tsai
2026-11-11 2:24 ` Ryan Brue [this message]
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