From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from outbound8.mail.transip.nl (outbound8.mail.transip.nl [136.144.136.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26D12301474; Sun, 31 May 2026 04:09:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=136.144.136.8 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780200584; cv=none; b=akw0N7I0VvJCHprJskKy2ftiMVjvJCPdNwCQzjGTNtqr3r9HUrFH3ILmYJiW2QPou5ZTa//AhrdTExJqhUFgbtoxe55Xd20hd/iJSzivDjcmOs1l4rL7MPKD5Q7bCJ2vuizuSawF6dFIShebENPTJFlxkWuMJcjOiI2CMVUsjYA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780200584; c=relaxed/simple; bh=mkFRdKwuUVef8l5jbZHd4TpVbtwCreqS1Vrc2PF1iTk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RAl8L+tj8vdaE5+Kl7+VuojgNhlyEvJn8W4+flCgPXUfsxfndbnMkyzh7S09CKJiMROID4YNAkQG2XqYspytFMxWfrA+gqSP18/9VWg7X/VJa7dAx8bTgdg8pmK0n4OY3RJ3z3imzqyjEJPeFB6Pss9GcM2K85natVfCrzWoix8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=herrie.org; spf=pass smtp.mailfrom=herrie.org; dkim=pass (2048-bit key) header.d=herrie.org header.i=@herrie.org header.b=j3F/qH3G; arc=none smtp.client-ip=136.144.136.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=herrie.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=herrie.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=herrie.org header.i=@herrie.org header.b="j3F/qH3G" Received: from submission4.mail.transip.nl (unknown [10.103.8.155]) by outbound8.mail.transip.nl (Postfix) with ESMTP id 4gSkB84xfdzY75qw; Sun, 31 May 2026 06:09:20 +0200 (CEST) Received: from herrie-desktop.. (180-93-184-31.ftth.glasoperator.nl [31.184.93.180]) by submission4.mail.transip.nl (Postfix) with ESMTPA id 4gSkB74hLfz3R3nyZ; Sun, 31 May 2026 06:09:19 +0200 (CEST) From: Herman van Hazendonk To: Amit Kucheria , Conor Dooley , Daniel Lezcano , devicetree@vger.kernel.org, Krzysztof Kozlowski , Lee Jones , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Lukasz Luba , "Rafael J. Wysocki" , Rob Herring , Satya Priya , Thara Gopinath , van Hazendonk , Zhang Rui Subject: [PATCH v2 2/3] dt-bindings: thermal: qcom: add pm8901-temp-alarm Date: Sun, 31 May 2026 06:09:15 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: ClueGetter at submission4.mail.transip.nl DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=transip-a; d=herrie.org; t=1780200560; h=from:subject:to:references: in-reply-to:date:mime-version; bh=idL6XwhXReC/2NUZIyb2R5aJeN5I6jIlHbCIEZ5aS2Y=; b=j3F/qH3GILh68AXwuwsdOUBCZcWNCDR3KoPHPg/rPJYAx4zAnX27ZkPCLBcSDbiXY9UZRm Fv7k6p8fM7Mo7rzq8DhzLcrpiEmIkC5JTGjGcAguzKxN3uKpfE87zipVKoDoZTFesVFPyy ZjbmPlhBEEOSFYssHpj1J2co4irXybgu71oFCrxdtbXSBhgKToSgwIX03kRzLLXQPYnQJ1 BvI4m1cxnIO78rkcOhElKPQrYVtOTjVk5nCv29TppZXy9pVwKFzx/xmn5s/XPS+R2qkuuF qb1+/OjHvNGXuaUBTVzmv7DrcrKcxalf17dz50KU5Mr3GwwKmoBevITWrUsd2w== X-Report-Abuse-To: abuse@transip.nl Add the binding for the temperature-alarm block inside the Qualcomm PM8901 PMIC (companion to the PM8058 on MSM8x60). The block has four selectable thresholds and three escalating stages; the driver maps these to representative millicelsius readings exposed to the thermal-of framework, and a board DT can wire stage 3 as a critical trip so the kernel issues orderly_poweroff() when the part overheats. The binding describes the SSBI sub-node address (CTRL register offset) and the two PMIC-internal interrupts the alarm raises: - TEMP_ALARM (PM8901 IRQ block 6 bit 4 == hwirq 52), asserted on every stage transition; - TEMP_HI_ALARM (PM8901 IRQ block 6 bit 5 == hwirq 53), asserted when the high-temperature stage is reached. The interrupts are sourced from the parent qcom,pm8901 PMIC's own interrupt-controller (not the SoC GIC); the node references the core /schemas/thermal/thermal-sensor.yaml so that the standard #thermal-sensor-cells handling and other shared thermal-sensor constraints are inherited automatically. Signed-off-by: Herman van Hazendonk --- .../thermal/qcom,pm8901-temp-alarm.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom,pm8901-temp-alarm.yaml diff --git a/Documentation/devicetree/bindings/thermal/qcom,pm8901-temp-alarm.yaml b/Documentation/devicetree/bindings/thermal/qcom,pm8901-temp-alarm.yaml new file mode 100644 index 000000000000..5d9eaeab8326 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom,pm8901-temp-alarm.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom,pm8901-temp-alarm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PM8901 PMIC Temperature Alarm + +maintainers: + - Herman van Hazendonk + +description: | + PM8901 is a secondary PMIC paired with PM8058 on MSM8x60 family + (MSM8260/MSM8660/APQ8060) platforms. It exposes an over-temperature + alarm block at SSBI offset 0x23 (CTRL) with four selectable + thresholds and three escalating stages. + + Unlike PM8058, there is no raw die-temperature ADC channel - the + driver decodes the stage + threshold pair into a representative + millicelsius value reported via the thermal-of framework. + + Two PMIC-internal interrupts are exposed: + + - TEMP_ALARM (PM8901 IRQ block 6 bit 4 == hwirq 52): asserted + on every stage transition; + - TEMP_HI_ALARM (PM8901 IRQ block 6 bit 5 == hwirq 53): asserted + when the part enters the high-temperature stage. + + Both line up on the parent qcom,pm8901 interrupt-controller. + +allOf: + - $ref: /schemas/thermal/thermal-sensor.yaml# + +properties: + compatible: + const: qcom,pm8901-temp-alarm + + reg: + description: SSBI offset of the temp-alarm CTRL register. + maxItems: 1 + + interrupts: + items: + - description: Stage-transition alarm interrupt (TEMP_ALARM). + - description: Hi-temperature alarm interrupt (TEMP_HI_ALARM). + + interrupt-names: + items: + - const: alarm + - const: hi-alarm + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + + ssbi { + #address-cells = <1>; + #size-cells = <0>; + + pmic@0 { + compatible = "qcom,pm8901"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&tlmm>; + interrupts = <31 IRQ_TYPE_EDGE_RISING>; + + temp-alarm@23 { + compatible = "qcom,pm8901-temp-alarm"; + reg = <0x23>; + interrupts = <52 IRQ_TYPE_EDGE_RISING>, + <53 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "alarm", "hi-alarm"; + #thermal-sensor-cells = <0>; + }; + }; + }; -- 2.43.0