Re: [PATCH] dt: arm64: qcom: sc8280xp-blackrock: amend usb0-sbu-mux enable gpio

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 5/17/26 1:59 PM, Dmitry Baryshkov wrote:
> On Mon, Jun 09, 2025 at 10:53:56PM +0200, Jens Glathe via B4 Relay wrote:
>> From: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
>>
>> The usb0 port didn't switch to dp altmode, investigation into DSDT
>> UCS0 device resulted into GPIO 100.
>>
>> Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
>> ---
>> This patch amends the enable gpio for the usb0-sbu-mux to the one
>> found in the DSDT file for this box. It shows a list of GPIOs in 
>> a certain order, and it has 2 buffers with conflicting values. 
>> The one deviating is in the second buffer, at the place where one 
>> would expect the GPIO for the select pin of USB0 (by pattern 
>> application from USB1). The GPIO previously used is also there, but 
>> at the end of the UCS0 buffer structure). Changing it resulted in 
>> a working dp altmode functionality on usb0.
>>
>> This debug effort is a result of work / testing of the 4-lanes patch
>> [1] on all available devices. Independent of it, it enables dp 
>> altmode on usb0, and with it, also 4 lanes, making it even more useful.
>>
>> [1]: https://lore.kernel.org/all/20250527-topic-4ln_dp_respin-v3-0-f9a0763ec289@oss.qualcomm.com/
>> ---
>>  arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> 
> P.S. Might it be that you need to set both GPIOs? Might the other GPIO
> be related to USB4 tunnelling?

On the CRD8280 schematic, GPIO_100 is N/C and there's a comment that
at some point SBU_SW_OE_N was moved from 100 to 101

Konrad