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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9084e4bf73sm424673566b.43.2026.02.24.05.19.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Feb 2026 05:20:00 -0800 (PST) Message-ID: Date: Tue, 24 Feb 2026 14:19:58 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 5/6] clk: qcom: Add support for Global clock controller on Eliza To: Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luca Weiss , Taniya Das , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov References: <20260223-eliza-clocks-v5-0-dcc66df713c3@oss.qualcomm.com> <20260223-eliza-clocks-v5-5-dcc66df713c3@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260223-eliza-clocks-v5-5-dcc66df713c3@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=O6A0fR9W c=1 sm=1 tr=0 ts=699da583 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=XWK_QsXDIVX7E2KYersA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: fwAmW5G5vxQT9e7cKuJV1NocleckLs5e X-Proofpoint-GUID: fwAmW5G5vxQT9e7cKuJV1NocleckLs5e X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI0MDEwNyBTYWx0ZWRfX/YuvU9a/2OGa 57sOPfM8OOMme/gGEnwLL8ppsJtfaSO7J8lw9Mtz/OnhYCHP44Cb+Z9xPEgSY6bRpPI8u/dfIr6 3Ib5czltjD8UIeFJnuo1QaSQPKZBoMRREcPoRZFgTv/Wb7jyLQNgpcE+EQAjaQi8UA8X2uGVr// vCAMrxG/xp/+QXpWd1zj3EM8paS6V6hVrrYu7MMoTjZtA27xR2onYT8to4h5/JTN0w7N55t/PXY uir0e+2k4OEm97tcGkRayV2QCdKPHNKBdUKQQ9KZS2kl2o314Qp2AyRVzasfz7lZOxqtSGA/TSl LM3tjRuCdeXdMFQ1oTlUNAheh7K/+YJT2kbtKyetSfj/2Va1lgKq9pdmZlBBTg27DSxlL9QvmON nHuo/QrQFLbZEvV1Tpba2BM4/1MI24qs4YS6zWtXJqXwFd0SYN5wwGBk0HZ3XNq4Fu3rDstaObJ Leeeaj5Xgqxphxf2Z6g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-24_01,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 priorityscore=1501 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602240107 On 2/23/26 1:01 PM, Abel Vesa wrote: > From: Taniya Das > > Add support for Global clock controller for Eliza Qualcomm SoC. > > Signed-off-by: Taniya Das > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Abel Vesa > --- [...] > + [GCC_CAMERA_HF_AXI_SLP_STG_ARES] = { 0x26018, 4 }, > + [GCC_CAMERA_SF_AXI_SLP_STG_ARES] = { 0x26028, 4 }, > + [GCC_CAMERA_HF_AXI_SEL_SLP_STG_ARES] = { 0x26018, 5 }, > + [GCC_CAMERA_SF_AXI_SEL_SLP_STG_ARES] = { 0x26028, 5 }, These are different from the ones we discussed at https://lore.kernel.org/all/d6392cb9-9ab2-4743-a13f-7432ec03762c@oss.qualcomm.com/ but they are also sort of similar in nature.. bit 5 selects hw (0) vs sw (1) control and bit 4 is the sw vote for asserting (1) or de-asserting (0) the signal Let's drop these too until we have a clear path forward with these gone: Reviewed-by: Konrad Dybcio Konrad