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Sat, 15 Feb 2025 00:29:26 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51F0TPSM028360 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 15 Feb 2025 00:29:25 GMT Received: from [10.134.70.212] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 14 Feb 2025 16:29:24 -0800 Message-ID: Date: Fri, 14 Feb 2025 16:29:24 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 05/15] drm/msm/dpu: decide right side per last bit Content-Language: en-US To: Jun Nie , Rob Clark , "Abhinav Kumar" , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" CC: , , , References: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org> <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-5-9701a16340da@linaro.org> From: Jessica Zhang In-Reply-To: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-5-9701a16340da@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _RsY9CC0vj4yEI0teLxAF5HLY0rqmG94 X-Proofpoint-GUID: _RsY9CC0vj4yEI0teLxAF5HLY0rqmG94 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-14_10,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 malwarescore=0 clxscore=1015 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502150002 On 1/17/2025 8:00 AM, Jun Nie wrote: > Currently, only one pair of mixers is supported, so a non-zero counter > value is sufficient to identify the correct mixer within that pair. > However, future implementations may involve multiple mixer pairs. With > the current implementation, all mixers within the second pair would be > incorrectly selected as right mixer. To correctly select the mixer > within a pair, test the least significant bit of the counter. If the > least significant bit is not set, select the mixer as left one; > otherwise, select the mixer as right one for all pairs. > > Signed-off-by: Jun Nie > Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > index 7191b1a6d41b3..41c9d3e3e3c7c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > @@ -369,11 +369,10 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, > static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) > { > struct dpu_crtc_state *crtc_state; > - int lm_idx, lm_horiz_position; > + int lm_idx; > > crtc_state = to_dpu_crtc_state(crtc->state); > > - lm_horiz_position = 0; > for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) { > const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; > struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm; > @@ -384,7 +383,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) > > cfg.out_width = drm_rect_width(lm_roi); > cfg.out_height = drm_rect_height(lm_roi); > - cfg.right_mixer = lm_horiz_position++; > + cfg.right_mixer = lm_idx & 0x1; > cfg.flags = 0; > hw_lm->ops.setup_mixer_out(hw_lm, &cfg); > } > > -- > 2.34.1 >