Re: [PATCH v2 1/3] dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support

[Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>]

On 11/27/2024 9:23 AM, Marc Kleine-Budde wrote:
> On 26.11.2024 17:21:14, Ciprian Marian Costea wrote:
>> On 11/26/2024 5:19 PM, Marc Kleine-Budde wrote:
>>> On 26.11.2024 16:18:41, Marc Kleine-Budde wrote:
>>>> On 26.11.2024 17:15:10, Ciprian Marian Costea wrote:
>>>>>>>>>> +        interrupt-names:
>>>>>>>>>> +          items:
>>>>>>>>>> +            - const: mb_0-7
>>>>>>
>>>>>> I was wondering if it makes sense to have an interrupt name not
>>>>>> mentioning the exact mailbox numbers, so that the same interrupt name
>>>>>> can be used for a different IP core, too. On the coldfire SoC the 1st
>>>>>> IRQ handles mailboxes 0...15.
>>>>>>
>>>>>
>>>>> I am ok with proposing a more generic name for mailboxes in order to
>>>>> increase reusability among FlexCAN enabled SoCs.
>>>>> Further specific mailbox numbers could be mentioned in the actual
>>>>> S32G2/S32G3 dtsi flexcan node.
>>>>>
>>>>> One proposal could be:
>>>>> - mb-1: First Range of Mailboxes
>>>>> - mb-2: Second Range of Mailboxes
>>>>>
>>>>> Let me know if you agree to update as proposed in V3.
>>>>
>>>> Looks good to me!
>>>
>>> Or maybe start with "0", that makes it a bit easier to construct the
>>> names of the IRQ-names in a for loop.
>>>
>>> regards,
>>> Marc
>>>
>>
>> That makes sense. Thanks for the suggestion.
> 
> I think we're almost there. Now you can change patch 1 to
> platform_get_irq_byname(..., "mb-1");.
> 
> regards,
> Marc
> 

Yes, I will also include this change in V3. Thanks for your suggestion.

Best Regards,
Ciprian

> P.S.: Actual support for the mailboxes 64..127 or the extended FIFO can
> be added in a later patch.
>