From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752517AbeDJIAa (ORCPT ); Tue, 10 Apr 2018 04:00:30 -0400 Received: from smtprelay.synopsys.com ([198.182.60.111]:49379 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752272AbeDJIA2 (ORCPT ); Tue, 10 Apr 2018 04:00:28 -0400 Subject: Re: [PATCH v2 6/9] PCI: dwc: Define maximum number of vectors To: Lorenzo Pieralisi Cc: "bhelgaas@google.com" , "Joao.Pinto@synopsys.com" , "jingoohan1@gmail.com" , "kishon@ti.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" References: <20180409160356.GA14533@e107981-ln.cambridge.arm.com> From: Gustavo Pimentel Message-ID: Date: Tue, 10 Apr 2018 08:59:30 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180409160356.GA14533@e107981-ln.cambridge.arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Lorenzo, On 09/04/2018 17:03, Lorenzo Pieralisi wrote: > On Mon, Apr 09, 2018 at 10:41:15AM +0100, Gustavo Pimentel wrote: >> Adds a callback that defines the maximum number of vectors that can be use >> by the Root Complex. >> >> Since this is a parameter associated to each SoC IP setting, makes sense to >> be configurable and easily visible to future modifications. >> >> The designware IP supports a maximum of 256 vectors. > > I think that a DT property instead of a callback would have made more > sense - I struggle to see the point in defining a callback to initialize > a variable, this can be done in the generic dwc code (and a DT binding). The addition of this callback was done in MSI-X patch series before I take over the PCIe Designware driver responsibility. However I remember a thread in which this subject was discussed (see [1]), maybe this could bring some light about the motive why is was done like this. If you don't agree I can do patch after this series only focusing on this topic in order to do like to suggested. [1] -> https://www.spinics.net/lists/linux-pci/msg61835.html > > Lorenzo > >> Signed-off-by: Gustavo Pimentel >> --- >> Change v1->v2: >> - Nothing changed, just to follow the patch set version. >> >> drivers/pci/dwc/pcie-designware-plat.c | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c >> index 5382a7a..94da252 100644 >> --- a/drivers/pci/dwc/pcie-designware-plat.c >> +++ b/drivers/pci/dwc/pcie-designware-plat.c >> @@ -48,8 +48,14 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp) >> return 0; >> } >> >> +static void dw_plat_set_num_vectors(struct pcie_port *pp) >> +{ >> + pp->num_vectors = MAX_MSI_IRQS; >> +} >> + >> static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { >> .host_init = dw_plat_pcie_host_init, >> + .set_num_vectors = dw_plat_set_num_vectors, >> }; >> >> static int dw_plat_pcie_establish_link(struct dw_pcie *pci) >> -- >> 2.7.4 >> >> Regards, Gustavo