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Clearing both bits stops > the spurious interrupt status from re-asserting. > > Best regards, > Munique Feitoza Hi, Thanks for confirming. Can you please share: 1) your full kernel log 2) an acpidump 3) /sys/kernel/debug/gpio On a kernel bugzilla? I'd like to look at a few things. At least this sure *sounds* like a floating GPIO. Thanks,> > On Thu, Nov 5, 2026 at 5:18 AM Linus Walleij wrote: >> >> On Fri, Oct 30, 2026 at 8:50 PM Munique Feitoza >> wrote: >> >>> When do_amd_gpio_irq_handler() detects a spurious interrupt on a pin >>> that is not configured as an IRQ line (!gpiochip_line_is_irq()), it >>> currently only clears BIT(INTERRUPT_MASK_OFF) while leaving >>> BIT(INTERRUPT_ENABLE_OFF) set. Unlike amd_gpio_irq_disable(), leaving >>> INTERRUPT_ENABLE_OFF enabled allows the pin status bit to keep >>> re-asserting in WAKE_INT_STATUS_REG0/1. Clear both INTERRUPT_MASK_OFF >>> and INTERRUPT_ENABLE_OFF when disabling a spurious GPIO IRQ on both >>> main and RGPIO banks. >>> >>> Additionally, if no GPIO interrupt was handled (ret == false), return >>> early before acquiring gpio_dev->lock and writing EOI_MASK to >>> WAKE_INT_MASTER_REG. This avoids unnecessary MMIO accesses and spinlock >>> contention when the IRQ line is shared or asserted by an unhandled >>> spurious interrupt storm. >>> >>> Signed-off-by: Munique Feitoza >> >> Sashiko comments aside, we really need to put Mario on CC for >> AMD patches, Mario what about adding yourself to this MAINTAINERS >> entry: >> >> PIN CONTROLLER - AMD >> M: Basavaraj Natikar >> M: Shyam Sundar S K >> S: Maintained >> F: drivers/pinctrl/pinctrl-amd.c >> >> >> Yours, >> Linus Walleij