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Mon, 5 Oct 2026 12:31:06 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Mon, 5 Oct 2026 12:31:06 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , Cristian Prundeanu , Breno Leitao Subject: [PATCH v11 08/11] iommu/arm-smmu-v3-kexec: Implement is_attach_deferred() Date: Mon, 5 Oct 2026 12:30:51 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE1A:EE_|SA1PR12MB999107:EE_ X-MS-Office365-Filtering-Correlation-Id: 6cac33fc-79d1-4666-e009-08df2317448d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|23010399003|36860700016|1800799024|10067099003|56012099006|6133799003|11063799006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0KR530dFD15cPOJ0qc458X629KjNSbekDY90ssfOw2kWXkd2RZoDyqgASk7i8iCi5yKja3KPG4PNizOVZYdDn8cdqWO+GBIP/0IxALbGtDnyeNprESBuBz53WM6IM9wfdqzKjDU1jDjsb7e4UhcTaRqOXo1R/PeTFtPlc6hsGkdo4jzTpCGfZAjk/09s6/iN4gkNCo+LobKBwIucfjwFlkCR2sZwADtEt5nd3jeat9HXPkYRM5bMmr44NhHwy0YiLHScIib5Er89YEQ/dvsI6SV0WaDM49nhBwO+lL90CPtrrnRvtBuHzSORxhIcbMmeEW36mzlPIHyDUFn5MlWj0TDVe3MA+gBfCoiafwFE/8gqDJ0cJsYyMULIlrxHGcAgvYe0Fp2MZOMNaQRRWLxC5OrrzKc2lHxXxpPgG5lD/kAR7l8Z5OZ6kPjMygc3X45R X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2026 19:31:35.1091 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6cac33fc-79d1-4666-e009-08df2317448d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB999107 Though the kdump kernel adopts the crashed kernel's stream table, the iommu core will still try to attach each probed device to a default domain, which overwrites the adopted STE and breaks in-flight DMA from that device. Implement an is_attach_deferred() callback to prevent this. For each device that has STE.V=1 and STE.Cfg!=Abort in the adopted table, defer the default domain attachment, until the device driver explicitly requests it. Also, move arm_smmu_get_step_for_sid() to the header for the kdump function to use. Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Tested-by: Breno Leitao Tested-by: Cristian Prundeanu Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 23 +++++++++++++++++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c | 19 ++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 ++++++++----------- 3 files changed, 52 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index a1f947e7d9fe4..49604550e3b9f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1280,6 +1280,22 @@ int __arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_cmd *cmds, int n, bool sync); + +static inline struct arm_smmu_ste * +arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) +{ + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; + + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { + /* Two-level walk */ + return &cfg->l2.l2ptrs[arm_smmu_strtab_l1_idx(sid)] + ->stes[arm_smmu_strtab_l2_idx(sid)]; + } else { + /* Simple linear lookup */ + return &cfg->linear.table[sid]; + } +} + int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_cmd *cmds, int n, @@ -1318,6 +1334,7 @@ int arm_smmu_kdump_adopt_strtab(struct arm_smmu_device *smmu); int arm_smmu_kdump_adopt_deferred_l2_strtab(struct arm_smmu_device *smmu, u32 sid, phys_addr_t base, u32 span, struct arm_smmu_strtab_l2 **l2table); +bool arm_smmu_kdump_is_attach_deferred(struct arm_smmu_master *master); #else /* CONFIG_CRASH_DUMP */ static inline int arm_smmu_kdump_adopt_strtab(struct arm_smmu_device *smmu) { @@ -1331,6 +1348,12 @@ arm_smmu_kdump_adopt_deferred_l2_strtab(struct arm_smmu_device *smmu, u32 sid, { return -EOPNOTSUPP; } + +static inline bool +arm_smmu_kdump_is_attach_deferred(struct arm_smmu_master *master) +{ + return false; +} #endif /* CONFIG_CRASH_DUMP */ struct arm_vsmmu { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c index 22d997480db1c..8a76b8cb4ef0a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c @@ -697,4 +697,23 @@ int arm_smmu_kdump_adopt_strtab(struct arm_smmu_device *smmu) smmu->options &= ~ARM_SMMU_OPT_KDUMP_ADOPT; return ret; } + +bool arm_smmu_kdump_is_attach_deferred(struct arm_smmu_master *master) +{ + struct arm_smmu_device *smmu = master->smmu; + int i; + + for (i = 0; i < master->num_streams; i++) { + struct arm_smmu_ste *ste = + arm_smmu_get_step_for_sid(smmu, master->streams[i].id); + u64 ent0 = le64_to_cpu(ste->data[0]); + + /* Defer only when there might be in-flight DMAs */ + if ((ent0 & STRTAB_STE_0_V) && + FIELD_GET(STRTAB_STE_0_CFG, ent0) != STRTAB_STE_0_CFG_ABORT) + return true; + } + + return false; +} #endif /* CONFIG_CRASH_DUMP */ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 3ec49c1e16aa7..d301f313ba1aa 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3142,21 +3142,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, return 0; } -static struct arm_smmu_ste * -arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) -{ - struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; - - if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { - /* Two-level walk */ - return &cfg->l2.l2ptrs[arm_smmu_strtab_l1_idx(sid)] - ->stes[arm_smmu_strtab_l2_idx(sid)]; - } else { - /* Simple linear lookup */ - return &cfg->linear.table[sid]; - } -} - void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, const struct arm_smmu_ste *target) { @@ -4598,6 +4583,15 @@ static int arm_smmu_def_domain_type(struct device *dev) return 0; } +static bool arm_smmu_is_attach_deferred(struct device *dev) +{ + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + + if (master->smmu->options & ARM_SMMU_OPT_KDUMP_ADOPT) + return arm_smmu_kdump_is_attach_deferred(master); + return false; +} + static const struct iommu_ops arm_smmu_ops = { .identity_domain = &arm_smmu_identity_domain, .blocked_domain = &arm_smmu_blocked_domain, @@ -4606,6 +4600,7 @@ static const struct iommu_ops arm_smmu_ops = { .hw_info = arm_smmu_hw_info, .domain_alloc_sva = arm_smmu_sva_domain_alloc, .domain_alloc_paging_flags = arm_smmu_domain_alloc_paging_flags, + .is_attach_deferred = arm_smmu_is_attach_deferred, .probe_device = arm_smmu_probe_device, .release_device = arm_smmu_release_device, .device_group = arm_smmu_device_group, -- 2.43.0