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Wed, 15 Jan 2025 22:48:09 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50FMm7LJ030991 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Jan 2025 22:48:07 GMT Received: from [10.110.66.9] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 15 Jan 2025 14:48:07 -0800 Message-ID: Date: Wed, 15 Jan 2025 14:47:52 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] arm64: dts: qcom: sm8750: Add LLCC node To: Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Satya Durga Srinivasu Prabhala , Trilok Soni , , , References: <20250113-sm8750_llcc_master-v1-0-5389b92e2d7a@quicinc.com> <20250113-sm8750_llcc_master-v1-4-5389b92e2d7a@quicinc.com> <7jo242e674fsqbia7udid4abq4euofishstmix6m7xqzdgcqiy@3zukruizim4n> Content-Language: en-US From: Melody Olvera In-Reply-To: <7jo242e674fsqbia7udid4abq4euofishstmix6m7xqzdgcqiy@3zukruizim4n> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZGf16znHDdHh8JZ4QUnNvv9juI3-AfX- X-Proofpoint-ORIG-GUID: ZGf16znHDdHh8JZ4QUnNvv9juI3-AfX- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-15_09,2025-01-15_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 adultscore=0 spamscore=0 malwarescore=0 suspectscore=0 mlxlogscore=813 impostorscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501150162 On 1/14/2025 2:59 AM, Dmitry Baryshkov wrote: > On Mon, Jan 13, 2025 at 01:26:43PM -0800, Melody Olvera wrote: >> Add LLCC node for SM8750 SoC. >> >> Signed-off-by: Melody Olvera >> --- >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..3cd7b40bdde68ac00c3dbe7fb3f20ebb2ba27045 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> @@ -2888,6 +2888,17 @@ gem_noc: interconnect@24100000 { >> #interconnect-cells = <2>; >> }; >> >> + cache-controller@24800000 { >> + compatible = "qcom,sm8750-llcc"; >> + reg = <0x0 0x24800000 0x0 0x200000>, <0x0 0x25800000 0x0 0x200000>, >> + <0x0 0x24C00000 0x0 0x200000>, <0x0 0x25C00000 0x0 0x200000>, >> + <0x0 0x26800000 0x0 0x200000>, <0x0 0x26C00000 0x0 0x200000>; >> + reg-names = "llcc0_base", "llcc1_base", >> + "llcc2_base", "llcc3_base", >> + "llcc_broadcast_base", "llcc_broadcast_and_base"; >> + interrupts = ; >> + }; > PLease take a look at sm8650 and change your patch accordingly. > > NAK Apologies; the contents of this patch are very similar to sm8650, just different offsets. Only major diffs I see here are the node namde (cache-controller vs system-cache-controller) and the formatting (two regs/line vs one reg/line). Is there anything else you mean by this comment that I'm missing? Thanks, Melody > >> + >> nsp_noc: interconnect@320c0000 { >> compatible = "qcom,sm8750-nsp-noc"; >> reg = <0x0 0x320c0000 0x0 0x13080>; >> >> -- >> 2.46.1 >>