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Fri, 06 Jun 2025 02:56:38 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5562ucgJ026105 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 6 Jun 2025 02:56:38 GMT Received: from [10.239.133.242] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 5 Jun 2025 19:56:35 -0700 Message-ID: Date: Fri, 6 Jun 2025 10:56:33 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 4/7] coresight-tgu: Add TGU decode support To: Jonathan Cameron CC: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , , References: <20250529081949.26493-1-quic_songchai@quicinc.com> <20250529081949.26493-5-quic_songchai@quicinc.com> <20250529123204.00005b78@huawei.com> Content-Language: en-US From: songchai In-Reply-To: <20250529123204.00005b78@huawei.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: -KTZXwyQ4vCOer1Jwvm39QZv7-WdxDFI X-Authority-Analysis: v=2.4 cv=EPcG00ZC c=1 sm=1 tr=0 ts=684258e7 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=COk6AnOGAAAA:8 a=AYfyxP4j3TdDPRqpEJ4A:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: -KTZXwyQ4vCOer1Jwvm39QZv7-WdxDFI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA2MDAyNyBTYWx0ZWRfX6op8+FGKWe8x VDR0S3AmS4bW+JOLS73ua0oryDpRxmTxDWwyOuxnIJHxflYrQc0rPsVrWTVDpRapt8nJMLhIP1P elstbWr6e9eJCjLjhAp+FlKhkeLm18VYaty4CxmS8qcS4Q/gWr1O9A4K9C/IPMl1U7xgoNGa2I3 zvrv86erzQOSAs5WoRWUQWkNyqYKCFOc6GbZrV8EktFECuULIUKD4/Kuv9tv0MlsTbJ9lPGkCXv joNdkVh5Ma31v2N9iRm+dcn9StYg83cy5oxcBJvv6taRyygqee6SDPiYcj0mgo/Ty49X9grN0HF sXUz7iHZP0hF5ZEcp3ZzZ1C2E741ZFsiDuh41GwMXA6TGVjz9VyIOZRHXU+ElUj9c7dMBMIQt5N sV+Ja/bfPPuNbp+F2AvwXkEE9Uoiu5aBeibvSxLbInoFLl+TTbmRNm1YCLTOBLBhsIJYT73e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-06_01,2025-06-05_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 phishscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506060027 On 5/29/2025 7:32 PM, Jonathan Cameron wrote: > On Thu, 29 May 2025 16:19:45 +0800 > Songwei Chai wrote: > >> Decoding is when all the potential pieces for creating a trigger >> are brought together for a given step. Example - there may be a >> counter keeping track of some occurrences and a priority-group that >> is being used to detect a pattern on the sense inputs. These 2 >> inputs to condition_decode must be programmed, for a given step, >> to establish the condition for the trigger, or movement to another >> steps. >> >> Signed-off-by: Songwei Chai >> diff --git a/drivers/hwtracing/coresight/coresight-tgu.c b/drivers/hwtracing/coresight/coresight-tgu.c >> index 6dbfd4c604b1..8dbe8ab30174 100644 >> --- a/drivers/hwtracing/coresight/coresight-tgu.c >> +++ b/drivers/hwtracing/coresight/coresight-tgu.c >> @@ -21,13 +21,35 @@ static int calculate_array_location(struct tgu_drvdata *drvdata, >> + >> static int tgu_enable(struct coresight_device *csdev, enum cs_mode mode, >> void *data) >> { >> + int ret = 0; > From what can be seen here, looks like ret is always set, so no need to init. Would this initialization improve the determinism of the code? :-) >> struct tgu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> >> spin_lock(&drvdata->spinlock); >> @@ -150,11 +264,15 @@ static int tgu_enable(struct coresight_device *csdev, enum cs_mode mode, >> spin_unlock(&drvdata->spinlock); >> return -EBUSY; >> } >> - tgu_write_all_hw_regs(drvdata); >> + ret = tgu_write_all_hw_regs(drvdata); >> + >> + if (ret == -EINVAL) >> + goto exit; >> drvdata->enable = true; >> >> +exit: >> spin_unlock(&drvdata->spinlock); >> - return 0; >> + return ret; >> } >> diff --git a/drivers/hwtracing/coresight/coresight-tgu.h b/drivers/hwtracing/coresight/coresight-tgu.h >> index f07ead505365..691da393ffa3 100644 >> --- a/drivers/hwtracing/coresight/coresight-tgu.h >> +++ b/drivers/hwtracing/coresight/coresight-tgu.h >> enum operation_index { >> TGU_PRIORITY0, >> TGU_PRIORITY1, >> TGU_PRIORITY2, >> - TGU_PRIORITY3 >> + TGU_PRIORITY3, > And here is why the previous patch should definitely have had the , Thanks for your clarification. > >> + TGU_CONDITION_DECODE >> >> }; >>