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Thu, 05 Nov 2026 01:44:34 -0800 (PST) Received: from [192.168.0.167] ([51.37.126.136]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48fecac17c1sm8628740f8f.10.2026.11.05.01.44.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Nov 2026 01:44:33 -0800 (PST) Message-ID: Date: Thu, 5 Nov 2026 09:44:32 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] media: qcom: camss: Add support for SM8150 To: mail@andrewgigena.dev, Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org References: <20261104-sm8150-v7-4-rc1-camss-v1-0-7a9534a9a22f@andrewgigena.dev> <20261104-sm8150-v7-4-rc1-camss-v1-3-7a9534a9a22f@andrewgigena.dev> From: Bryan O'Donoghue Content-Language: en-GB In-Reply-To: <20261104-sm8150-v7-4-rc1-camss-v1-3-7a9534a9a22f@andrewgigena.dev> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 04/11/2026 20:54, Andrew Gigena via B4 Relay wrote: > The hardware reuses the existing 3-phase 1.0 CSIPHY, Gen2 CSID and > VFE 17x implementations; the CSIPHY uses the SC8280XP lane register > layout. Add CAMSS_8150 to the version enum and to the shared code > paths, then add the per-block clock, regulator, power domain, > interrupt and interconnect resources. That's odd. sm8150 and sm8250 are proximate both seven nanometers sc8280xp is five nanometers. PHYs are about converting the analog to the digital domain and so process geometery - ends up making a difference. You can get the PHY init sequences here: drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/ ├── cam_csiphy_core.c ├── cam_csiphy_soc.c ├── cam_csiphy_dev.h └── include/ ├── cam_csiphy_1_0_hwreg.h sdm845 ├── cam_csiphy_1_1_hwreg.h sm8150 ├── cam_csiphy_1_2_hwreg.h sm7150 └── cam_csiphy_1_2_1_hwreg.h kona/sm8250 https://git.codelinaro.org/clo/la/platform/vendor/opensource/camera-kernel/-/blob/LA.AU.1.3.7-02900-gen3_gvmgh.0/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h?ref_type=tags So yeah going by the name that's CSIPHY 1_1 same for sc8280xp and sm8150. Hmm so much for my understanding of how dependant on process node these sequences really are.. perhaps the PHYs area fully synthesizable in RTL, probably. Anyway. The one thing to do here is to please _verify_ what's upstream now against the tag provided there. If there is a divergence then we need to upstream a 8150 compliant version. ... Actually its fine, did the verification for you, the 1.1 init sequence as is upstream is fine. Just please tidy up the ordering of the 8150 switches. --- bod