From: Frieder Schrempf <frieder.schrempf@kontron.de>
To: Adam Ford <aford173@gmail.com>, linux-arm-kernel@lists.infradead.org
Cc: aford@beaconembeded.com, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/3] arm64: dts: imx8mm: Simplify mipi_dsi clocks
Date: Thu, 30 Nov 2023 16:42:53 +0100 [thread overview]
Message-ID: <a84b42eb-5543-4fff-ac92-bdf32cad1985@kontron.de> (raw)
In-Reply-To: <20231128045415.210682-1-aford173@gmail.com>
On 28.11.23 05:54, Adam Ford wrote:
> The device tree clock structure for the mipi_dsi is
> unnecessarily redundant.
>
> The default clock parent of IMX8MM_CLK_DSI_PHY_REF is
> already IMX8MM_CLK_24M, so there is no need to set the
> parent-child relationship between them. The default clock
> rates for IMX8MM_SYS_PLL1_266M and IMX8MM_CLK_24M are
> already defined to be 266MHz and 24MHz respectively,
> so there is no need to define those clock rates.
>
> On i.MX8M[MNP] the samsung,pll-clock-frequency is not
> necessary, because the driver will read it from sclk_mipi
> which is also already set to 24MHz making it also
> redundant.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 738024baaa57..8d872568231d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1151,12 +1151,8 @@ mipi_dsi: dsi@32e10000 {
> clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> <&clk IMX8MM_CLK_DSI_PHY_REF>;
> clock-names = "bus_clk", "sclk_mipi";
> - assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> - <&clk IMX8MM_CLK_DSI_PHY_REF>;
> - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> - <&clk IMX8MM_CLK_24M>;
> - assigned-clock-rates = <266000000>, <24000000>;
> - samsung,pll-clock-frequency = <24000000>;
> + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>;
> interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
> status = "disabled";
Thanks for the cleanup!
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL
i.MX8MM
next prev parent reply other threads:[~2023-11-30 15:43 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-28 4:54 Adam Ford
2023-11-28 4:54 ` [PATCH 2/3] arm64: dts: imx8mm: Remove video_pll1 clock rate from clk node Adam Ford
2023-11-30 15:46 ` Frieder Schrempf
2023-11-28 4:54 ` [PATCH 3/3] arm64: dts: imx8mm: Slow default video_pll1 clock rate Adam Ford
2023-11-30 15:46 ` Frieder Schrempf
2023-11-30 15:42 ` Frieder Schrempf [this message]
2023-12-06 2:17 ` [PATCH 1/3] arm64: dts: imx8mm: Simplify mipi_dsi clocks Shawn Guo
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