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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE1MDA0MSBTYWx0ZWRfX90ttUlHrWLEn KmCgp03RbJfnU4YD/n7fAdxwXo27jNyXPAjQOpsTLKd4OUJCtncw3+aq3YPbRiUTWGU4EnqmKAZ 8DRc6VpGdDTulJfnKD6V/aHNQmc5eD8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE1MDA0MSBTYWx0ZWRfX8kf6tpFjf9qP TsbkkPcF6ivICohefQU8bPwanvnO/s+TYA7ZR9EOvzlU5uEgwqPG4+eZX8P7u+YIuGV2Ff7jr4B LapIwP8XtHEIYB27jcYBc4QIYTS7bX9ffHktvwgNSxOjLkPXJo1oUXwIr+mkCjuTglYcT0/hPY6 17VuJFgvgBMyrsATF1KYdzmiBQ7te66S6tTIDCFQsO3A5SWF+5QqG6pyoe3pr86emVPsuZ8C7uC s8iu5u0uknpafbY0Ad99q9bLmEYAn65XRdGf9zilQ3DVhde1B9JNC7pP/fFkvQ0TR4h4Xi8eEl2 0PiDS8eGVVLZCveFWQ/zprkD2+Dh3+vI9NvbRqFEozjBaGkfkiwYiWDriv0lPUNKWW3VBHN5KRX Gd3iUrQ4O5TqjioH4iRmOwo4Kd+ueGq3FtkO6CQCgvX9vC7F7qlNqhjzxplh/DZLDSn6zo9KJsi CtkkLOT3YPyGUpnNzfQ== X-Authority-Analysis: v=2.4 cv=BNMmP1QG c=1 sm=1 tr=0 ts=6ad0aad3 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=AByBbePJZrCWKXECz8gA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: xBknP2ySgHbmwT0cQ3rKPluCupxbeekc X-Proofpoint-ORIG-GUID: xBknP2ySgHbmwT0cQ3rKPluCupxbeekc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-14_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610150041 On 9/29/26 4:08 PM, Shawn Guo wrote: > On Tue, Sep 29, 2026 at 09:57:40AM +0200, Krzysztof Kozlowski wrote: >> On Fri, Sep 25, 2026 at 12:11:50AM +0800, Shawn Guo wrote: >>> The schema describes exactly two clock inputs for every compatible it >>> covers, a board XO and a video AHB clock from GCC. That is only true >>> for part of the drivers bound to these compatibles. videocc-glymur.c, >>> which handles qcom,glymur-videocc and qcom,nord-videocc, and >>> videocc-sm8750.c both declare their DT inputs as DT_BI_TCXO, >>> DT_BI_TCXO_AO and DT_SLEEP_CLK, and parent video_cc_sleep_clk_src on >>> DT_SLEEP_CLK. >> >> I don't understand what you are saying here. You are mixing drivers and >> compatibles. > > You are right! The argument was the wrong way round. What I should have > written for a schema is the hardware, not the Linux driver. Sorry about > that. > > Per the hardware documentation, the video clock controller on Glymur, > Nord and SM8750 has three clock inputs: the board XO, the always-on board > XO that feeds its PLL reference, and the 32 kHz chip sleep clock that > sources its sleep clock generator. There is no AHB clock input > on the block; the AHB clock the controller uses for itself is generated > internally from the XO input. I'm staring at the document and my interpretation of it is that the AHB clock provides bus access to the controller (via the AHB2AHB bridge). Konrad