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Thu, 25 Jun 2026 21:16:09 -0700 (PDT) X-Received: by 2002:a05:693c:88c7:20b0:30c:9f31:b619 with SMTP id 5a478bee46e88-30c9f31c303mr424875eec.12.1782447369035; Thu, 25 Jun 2026 21:16:09 -0700 (PDT) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30c7c4c691dsm13065050eec.5.2026.06.25.21.16.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jun 2026 21:16:08 -0700 (PDT) Message-ID: Date: Fri, 26 Jun 2026 09:46:03 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes To: Abel Vesa Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260610-eliza_dt-v1-1-7bb72b75fc5b@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI2MDAzMCBTYWx0ZWRfX/1bF5KZaJR3q trEzjFs+XO3+9eeYPFT2qASzZVoUnij6YsA4mTr7cAkAD5F3Tlt7xb0QBQKO1hQG72MOtWDYi35 9fdsTAefnZreMTyOy0x6zmbvlfB0x9YfP/2sFsoTXvNOy0nWt+LNbJqjopYZRGn+FCZWQ1sWQ3K cRZH+j+tKDODG6tn6DE8TpgQTu6+vxbAHSxSO2/uAGlp5M17YZnjr44B0BuvY9d21YUI5BcQlqw SENBIwm+5E6PArVCpd69HxaDgq7D7Fst9jVCZAB6jAAXx74/kH/37OcY80tS4OniM2WMjIlb7nv ISkiV7/18JE65fQrkzJxNbotvVnxcdQBCZ/qSth+VB06HEFbNEGCNpzJej/fwJez59ASCprfC7Q 3zJdLJC97Dhn64CjB/D6UJhFHEfiKBvAkW7XIKmQ48WSGKsX6WZa2DH62d8wSQcf6HeZPTT/kZf cS36E75VH64Kfh9Ledw== X-Proofpoint-ORIG-GUID: -WaGMNW9-RO2OlNCr8OdX2g3Q-UkBr8i X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI2MDAzMCBTYWx0ZWRfX6pZ2wqZwJOGm JOSskU4JF/AfX1+7Oqik0HvNU0cbQk1vYaSExuOrlDelU9zvB2I7PfQkIAe9C5I+rxHorihft6d dmK6ffejF4fu47iUWJZUI5x5UkJ1O1g= X-Authority-Analysis: v=2.4 cv=daqwG3Xe c=1 sm=1 tr=0 ts=6a3dfd0a cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=SQ51kRXigZCXnAXuiy8A:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: -WaGMNW9-RO2OlNCr8OdX2g3Q-UkBr8i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-26_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 suspectscore=0 bulkscore=0 adultscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606260030 On 6/25/2026 3:42 PM, Abel Vesa wrote: > On 26-06-10 17:40:09, Krishna Chaitanya Chundru wrote: >> Eliza supports two PCIe instances: one 8GT/s x1 (PCIe0) and one 8GT/s x2 >> (PCIe1). Add PCIe controller and PHY nodes for both instances, and update >> the GCC clock references to use the newly added PHY nodes instead of >> placeholder zeros. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> This patch depends on https://lore.kernel.org/all/20260608-eliza-v3-0-9bdeb7434b28@oss.qualcomm.com/ >> --- >> arch/arm64/boot/dts/qcom/eliza.dtsi | 359 +++++++++++++++++++++++++++++++++++- >> 1 file changed, 357 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi >> index 7e97361a5dc5..2a51da62270d 100644 >> --- a/arch/arm64/boot/dts/qcom/eliza.dtsi >> +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi >> @@ -610,8 +610,8 @@ gcc: clock-controller@100000 { >> >> clocks = <&bi_tcxo_div2>, >> <&sleep_clk>, >> - <0>, >> - <0>, >> + <&pcie0_phy>, >> + <&pcie1_phy>, >> <&ufs_mem_phy 0>, >> <&ufs_mem_phy 1>, >> <&ufs_mem_phy 2>, >> @@ -716,6 +716,361 @@ mmss_noc: interconnect@1780000 { >> #interconnect-cells = <2>; >> }; >> >> + pcie0: pcie@1c00000 { >> + device_type = "pci"; >> + compatible = "qcom,eliza-pcie", "qcom,pcie-sm8550"; >> + reg = <0 0x01c00000 0 0x3000>, >> + <0 0x40000000 0 0xf1d>, >> + <0 0x40000f20 0 0xa8>, >> + <0 0x40001000 0 0x1000>, >> + <0 0x40100000 0 0x100000>, >> + <0 0x01c03000 0 0x1000>; >> + reg-names = "parf", >> + "dbi", >> + "elbi", >> + "atu", >> + "config", >> + "mhi"; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, >> + <0x02000000 0 0x40300000 0 0x40300000 0 0x3d00000>; >> + >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + interrupt-names = "msi0", >> + "msi1", >> + "msi2", >> + "msi3", >> + "msi4", >> + "msi5", >> + "msi6", >> + "msi7", >> + "global"; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, >> + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, >> + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, >> + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a", >> + "ddrss_sf_tbu", >> + "noc_aggr", >> + "cnoc_sf_axi"; >> + >> + resets = <&gcc GCC_PCIE_0_BCR>, >> + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; >> + reset-names = "pci", >> + "link_down"; >> + >> + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; >> + interconnect-names = "pcie-mem", >> + "cpu-pcie"; >> + >> + power-domains = <&gcc GCC_PCIE_0_GDSC>; >> + >> + operating-points-v2 = <&pcie0_opp_table>; >> + >> + iommu-map = <0 &apps_smmu 0x1480 0x1>, >> + <0x100 &apps_smmu 0x1481 0x1>; >> + >> + interrupt-map = <0 0 0 1 &intc 0 0 0 564 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 2 &intc 0 0 0 565 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 3 &intc 0 0 0 566 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 4 &intc 0 0 0 567 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-map-mask = <0 0 0 0x7>; >> + #interrupt-cells = <1>; >> + >> + linux,pci-domain = <0>; >> + num-lanes = <1>; >> + bus-range = <0 0xff>; >> + >> + dma-coherent; >> + > No pinctrl states? > >> + >> + pcie1: pcie@1c08000 { >> + device_type = "pci"; >> + compatible = "qcom,eliza-pcie", "qcom,pcie-sm8550"; >> + reg = <0 0x01c08000 0 0x3000>, >> + <0 0x44000000 0 0xf1d>, >> + <0 0x44000f20 0 0xa8>, >> + <0 0x44001000 0 0x1000>, >> + <0 0x44100000 0 0x100000>, >> + <0 0x01c0b000 0 0x1000>; >> + reg-names = "parf", >> + "dbi", >> + "elbi", >> + "atu", >> + "config", >> + "mhi"; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0 0x00000000 0 0x44200000 0 0x100000>, >> + <0x02000000 0 0x44300000 0 0x44300000 0 0x3d00000>; >> + >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + interrupt-names = "msi0", >> + "msi1", >> + "msi2", >> + "msi3", >> + "msi4", >> + "msi5", >> + "msi6", >> + "msi7", >> + "global"; >> + >> + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, >> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, >> + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, >> + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, >> + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a", >> + "ddrss_sf_tbu", >> + "noc_aggr", >> + "cnoc_sf_axi"; >> + >> + resets = <&gcc GCC_PCIE_1_BCR>, >> + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; >> + reset-names = "pci", >> + "link_down"; >> + >> + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; >> + interconnect-names = "pcie-mem", >> + "cpu-pcie"; >> + >> + power-domains = <&gcc GCC_PCIE_1_GDSC>; >> + >> + operating-points-v2 = <&pcie1_opp_table>; >> + >> + iommu-map = <0 &apps_smmu 0x1400 0x1>, >> + <0x100 &apps_smmu 0x1401 0x1>; >> + >> + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-map-mask = <0 0 0 0x7>; >> + #interrupt-cells = <1>; >> + >> + linux,pci-domain = <1>; >> + num-lanes = <2>; >> + bus-range = <0 0xff>; >> + >> + dma-coherent; > No pinctrl states? As we are adding perst & wake gpio's in board specific file, it is better to add the pincntrl also there only. - Krishna Chaitanya.