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Thu, 02 Oct 2025 03:06:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEcKiWJW5aLjMg3oNcuCPIVwZjr+gQ1x/JxWytHkyrPwo2mPMeoJLrZ9O10AaPCw0B12SvaNw== X-Received: by 2002:a05:6a20:e614:b0:2f0:4f71:c482 with SMTP id adf61e73a8af0-321d8452aa2mr9556469637.1.1759399589951; Thu, 02 Oct 2025 03:06:29 -0700 (PDT) Received: from [10.204.101.186] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-78b01f9cda9sm1861043b3a.13.2025.10.02.03.06.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Oct 2025 03:06:29 -0700 (PDT) Message-ID: Date: Thu, 2 Oct 2025 15:36:24 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 4/8] media: iris: Introduce buffer size calculations for vpu4 Content-Language: en-US To: Bryan O'Donoghue , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vishnu Reddy References: <20250925-knp_video-v1-0-e323c0b3c0cd@oss.qualcomm.com> <20250925-knp_video-v1-4-e323c0b3c0cd@oss.qualcomm.com> From: Vikash Garodia In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=OJoqHCaB c=1 sm=1 tr=0 ts=68de4ea7 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=rPdB782uDU9_FGz_shsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI3MDAzMiBTYWx0ZWRfXwityTFOrlqhN fDKme/WgXGWmvHsANGchV/MbTA17ncvcrcuyZzynzPN4w98mUZIhAFd1srCDUXYsn6kPreLIusL jXZDx9GK0AwQ+KODspHikuX8QaWp+INC8tXvccZSVa+K0cdnAdsdc+fmzcqe7+V6KcfYYLlxF8S DSqCAmQRUcIDdGKo6fal7TD3z6DayznljvjCCPpQHsD6fO2jjK1f2wKjsBIk4US6motnxBh75La 8yrIFN3vhD8yH7lclcEhbcb59w3HI/gwMNybakHQtB7bydaEQPgfmSXU9ao26lMYuyfVjKnoaqt 5Wv4wUFJw4EvOsaMmLZBa5b+kgYW0ChVH3qdBnGCILjCo52eM/tFCBkySOrovmzhYv6GsEqQ6ZC KCTrxijpTBT1QKhZaxx3eyHzXge4aw== X-Proofpoint-ORIG-GUID: 3ly8Z7_Gl5waOlrr3ER8vt8flwrzuD3a X-Proofpoint-GUID: 3ly8Z7_Gl5waOlrr3ER8vt8flwrzuD3a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-02_03,2025-10-02_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509270032 On 9/26/2025 6:30 PM, Bryan O'Donoghue wrote: > On 25/09/2025 00:14, Vikash Garodia wrote: >> +{ >> +    u32 dma_opb_wr_tlb_y_size = ((frame_width_coded + 15) >> 4) << 7; >> +    u32 dma_opb_wr_tlb_uv_size = ((frame_width_coded + 15) >> 4) << 7; >> +    u32 dma_opb_wr2_tlb_y_size = ALIGN((2 * 6 * 64 * frame_height_coded / 8), >> DMA_ALIGNMENT) * >> +                       num_vpp_pipes_enc; >> +    u32 dma_opb_wr2_tlb_uv_size = ALIGN((2 * 6 * 64 * frame_height_coded / >> 8), DMA_ALIGNMENT) * >> +                        num_vpp_pipes_enc; > > I find these calculations pretty nebulous and not very obvious to look at. > > A define of some sort with a comment would definitely help other programmers > reviewing and supporting this code in the future. > > (+ 15 >> 4) << 7 - I'm sure it makes sense when you are looking at a register > spec in front of your eyes but if you don't have that detail its pretty hard to > say the values are correct. > > /* >  * SET_Y_SIZE(x) >  *     - Add 15 because >  *     - Shift 4 to lower nibble because >  *     - Shift the result up 7 because >  */ > #define SET_Y_SIZE(x) > Sure, i would trying to gather and explain as much info feasible from my side. At the same time, these calculation for hardware internal buffers have been there for vpu2/3x, and is being extended for vpu4 in a similar way. Regards, Vikash