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Mon, 12 Oct 2026 09:02:12 -0700 (PDT) X-Received: by 2002:a05:622a:110a:b0:535:1a6:6e93 with SMTP id d75a77b69052e-5359f4e01bfmr192064921cf.2.1791820931537; Mon, 12 Oct 2026 09:02:11 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c353bf3a541sm110415666b.25.2026.10.12.09.02.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Oct 2026 09:02:10 -0700 (PDT) Message-ID: Date: Mon, 12 Oct 2026 18:02:08 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/4] arm64: dts: qcom: qcs6490-rb3gen2: add the clock controller To: Alex Elder , sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org Cc: abelvesa@kernel.org, kees@kernel.org, gustavoars@kernel.org, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, danielt@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Thompson References: <20261012152408.3729237-1-elder@riscstar.com> <20261012152408.3729237-5-elder@riscstar.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261012152408.3729237-5-elder@riscstar.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEyMDA2MyBTYWx0ZWRfX/MPnnPlNgwjc ymS2XWpzw7hw8xYgzc9vAoBi5y1QBdf8h9FPfot9bOgC5CwpbXI4TLBNgfiEQE67Wr6t6rvdV3y vpwl9vJ12q5BEKHONugkOOWwosV2RTzop++z0wS3Nw1sT9b6/soU8LAxj2fahE+MoLB1w/XXr1P hs0+Hcid5uYgYqM+tf8csr1zeksvNbzSDmq4oCjLdnUMoQoWerNoWOC0Gs/zV7CzQJ4drfzDxdr DuptvX5vDjlQPea8KqC2bHaUOUDrmyxRFyMuH8M3tpDJSWFzG4CP535J/l8U9SwK7cZVEzRoCpS qBdZQ3FXngWYSOAjDVR79LSYNXLhSMkCv9BYDbkDQLukEEDkVuAHkc3QGQGyMjaYlEF2fsac+1c 3RAVWDrmuSLe9Aw5P0T60Dsgsw98CKyA1kH6aeZoxdQGcBbsqBtsJbz5vsr/AgtUcMBB4+Rv38M I77NPKX1QqzqdENci6A== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEyMDA2MyBTYWx0ZWRfX1WHXFPrj9xcI poWuFc1x93yblshoXgkRdQcDMCUaS/iU9yVN+ih9dl9Q+LqVH3+FwbQyhX1VSNrSYz2f2LCbqEf O5DEe0r83uy0sg78gQh4Oku3EZbHf7M= X-Authority-Analysis: v=2.4 cv=VOtIDNPX c=1 sm=1 tr=0 ts=6acd0485 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=ee_2aqc6AAAA:8 a=WjKZ7VJ2YQ59rNZOuecA:9 a=QEXdDO2ut3YA:10 a=zZCYzV9kfG8A:10 a=dawVfQjAaf238kedN5IG:22 a=VOpmJXOdbJOWo2YY3GeN:22 X-Proofpoint-GUID: X4hVaceGwHtC8LMo__7vPYufmn-B4JVC X-Proofpoint-ORIG-GUID: X4hVaceGwHtC8LMo__7vPYufmn-B4JVC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-12_05,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 clxscore=1015 bulkscore=0 phishscore=0 spamscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610120063 On 10/12/26 5:24 PM, Alex Elder wrote: > The clock controller within the TC9564 SoC is accessed via a PCI > endpoint bus through BAR 4 of the first embedded PCIe function. > A syscon node is created to provide access to a range of memory > that is used by the clock controller and shared with other devices. > > Co-developed-by: Daniel Thompson > Signed-off-by: Daniel Thompson > Signed-off-by: Alex Elder > --- [...] > +&pcie_s1b5d0f0_bar4_bus { > + syscon@0 { > + compatible = "syscon", "simple-mfd"; > + reg = <0x0 0x2000>; > + > + tc9564_clock0: clock-controller { > + compatible = "toshiba,tc9564-clock"; > + clocks = <&tc9564_xo_board>; > + #clock-cells = <1>; > + }; > + }; It's the same file - just put the node under the ep-bus definition Konrad