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Wed, 9 Jul 2025 00:51:32 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 9 Jul 2025 00:51:32 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 9 Jul 2025 00:51:32 -0500 Received: from [172.24.227.245] (uda0132425.dhcp.ti.com [172.24.227.245]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5695pRhx3408594; Wed, 9 Jul 2025 00:51:28 -0500 Message-ID: Date: Wed, 9 Jul 2025 11:21:15 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 3/4] arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs To: Rob Herring , Paresh Bhagat CC: , , , , , , , , , , , , , , References: <20250708085839.1498505-1-p-bhagat@ti.com> <20250708085839.1498505-4-p-bhagat@ti.com> <20250708202259.GA904737-robh@kernel.org> From: Vignesh Raghavendra Content-Language: en-US In-Reply-To: <20250708202259.GA904737-robh@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Hi Rob, On 09/07/25 01:52, Rob Herring wrote: > On Tue, Jul 08, 2025 at 02:28:38PM +0530, Paresh Bhagat wrote: >> Update k3-pinctrl file to include pin definitions for AM62D2 family of >> SoCs. >> >> Signed-off-by: Paresh Bhagat >> Reviewed-by: Devarsh Thakkar >> --- >> arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h >> index cac7cccc1112..0cf57179c974 100644 >> --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h >> +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h >> @@ -63,6 +63,9 @@ >> #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) >> #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) >> >> +#define AM62DX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) >> +#define AM62DX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) >> + >> #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) >> #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) > > Why is the same expression just repeated over and over? Looks like this > needs some refactoring. > Is the comment wrt having another common macro (for better code reuse) for the right hand side here? Or is the comment wrt having differently named macros for each SoCs? Having per SoC macro is intentional so to avoid backward compatibility issues when these SoC macros deviate in future -- Regards Vignesh https://ti.com/opensource