From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m32105.qiye.163.com (mail-m32105.qiye.163.com [220.197.32.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3351D38BF62 for ; Mon, 1 Jun 2026 10:50:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.105 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780311044; cv=none; b=fVzvcf72tAvOYFzs0fMen0SiQN0CyqeMHvgmkHIiczuzOnLCch3QbqDVbbk8ZGgam6sCMyA55Lwd5wTo3FRE57nXDtbj3NHOl6sszxiOsmjgCveUyDjeLGYUidEZJseM+nNE+N6EttzwGrRsw1S+OreLkWSZBBn4HAeuD5E7XIQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780311044; c=relaxed/simple; bh=c8Omhdi6b0oVxQ3D3+ocHwwVuReXHmJbIss8VTKuzpw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=KsCEjr7IFPJTHQ8Mee2VdOdrqRjqko6UDRmWRxu4jsYu4SHWWjj1x1tTWHEXgRqdJjG2xRxFyAOxVnMjyaFoULbBVktCqY+m1OLbaVyY6HHX2R9W144mJxVVmiyG8q2870OsiekzQFH6UVq+a2SuDIaSpgJZt9okph2GZ3+NjRc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=BfXqXNyo; arc=none smtp.client-ip=220.197.32.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="BfXqXNyo" Received: from [172.16.12.77] (unknown [61.154.14.86]) by smtp.qiye.163.com (Hmail) with ESMTP id 4097835ba; Mon, 1 Jun 2026 18:45:28 +0800 (GMT+08:00) Message-ID: Date: Mon, 1 Jun 2026 18:45:28 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] drm/rockchip: vop2: Wait for layer cfg done before switching LAYERSEL_REGDONE_SEL To: Cristian Ciocaltea , Sandy Huang , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260504-vop2-layer-cfg-tmout-v1-0-730226a7331e@collabora.com> <20260504-vop2-layer-cfg-tmout-v1-2-730226a7331e@collabora.com> Content-Language: en-US From: Andy Yan In-Reply-To: <20260504-vop2-layer-cfg-tmout-v1-2-730226a7331e@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-HM-Tid: 0a9e82c9e0e709d8kunmad12aac138cee1 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVlDGUxKVk1JHhlCQ01KTkxLSFYVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU 9PT0hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=BfXqXNyopum9m3NwZ3/eLvgDX/aWRtwx81UaXfNhBs/h5/HxoDhhncez6cfRAWAHnc/Vwd9lvbGj6wLRIWR3Ylgs82gcHezYHfcWMPBEzr5O5UuzfgX21toLVYA6gNXbgvCqBBq6keqTxKZGXDLBosAcXbIMOL+FUBNHcP/azD0=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=szKM+xo2CtG53S4RQ+h02A+npZXUcLB6AowO29QwZPs=; h=date:mime-version:subject:message-id:from; Hello, On 5/5/26 02:24, Cristian Ciocaltea wrote: > LAYERSEL_REGDONE_SEL mask of RK3568_OVL_CTRL register controls which > Video Port (VP) vsync latches the shared RK3568_OVL_{LAYER|PORT}_SEL > shadow registers into the active configuration. > > rk3568_vop2_setup_layer_mixer() overwrites LAYERSEL_REGDONE_SEL to the > current VP ID before waiting for the previous VP layer configuration to > take effect. As a consequence, the previous VP vsync can no longer > trigger the latch, so the wait polls a value that might never appear. > > Move the layer cfg done wait before the RK3568_OVL_CTRL write so the > previous VP vsync can still commit the pending configuration. > > Fixes: 3e89a8c68354 ("drm/rockchip: vop2: Fix the update of LAYER/PORT select registers when there are multi display output on rk3588/rk3568") > Signed-off-by: Cristian Ciocaltea Reviewed-by: Andy Yan > --- > drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 19 ++++++++++--------- > 1 file changed, 10 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c > index edca0fb16e08..5206f01ec787 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c > @@ -2289,15 +2289,6 @@ static void rk3568_vop2_setup_layer_mixer(struct vop2_video_port *vp) > * lead to the configuration of the previous VP being take effect along with the VSYNC > * of the new VP. > */ > - if (layer_sel != old_layer_sel || port_sel != old_port_sel) > - ovl_ctrl |= FIELD_PREP(RK3568_OVL_CTRL__LAYERSEL_REGDONE_SEL, vp->id); > - vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl); > - > - if (port_sel != old_port_sel) { > - vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); > - vop2_cfg_done(vp); > - rk3568_vop2_wait_for_port_mux_done(vop2); > - } > > if (layer_sel != old_layer_sel && atv_layer_sel != old_layer_sel) { > cfg_done = vop2_readl(vop2, RK3568_REG_CFG_DONE); > @@ -2310,6 +2301,16 @@ static void rk3568_vop2_setup_layer_mixer(struct vop2_video_port *vp) > rk3568_vop2_wait_for_layer_cfg_done(vop2, old_layer_sel); > } > > + if (layer_sel != old_layer_sel || port_sel != old_port_sel) > + ovl_ctrl |= FIELD_PREP(RK3568_OVL_CTRL__LAYERSEL_REGDONE_SEL, vp->id); > + vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl); > + > + if (port_sel != old_port_sel) { > + vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); > + vop2_cfg_done(vp); > + rk3568_vop2_wait_for_port_mux_done(vop2); > + } > + > vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); > mutex_unlock(&vop2->ovl_lock); > } >