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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d0228417adsm11343225ad.0.2026.07.29.06.15.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Jul 2026 06:15:48 -0700 (PDT) Message-ID: Date: Wed, 29 Jul 2026 21:15:42 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/12] clk: qcom: ipq-cmn-pll: Add NSS clock support To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> <20260724-qcom_ipq5210_cmnpll-v1-4-a8b8679d215f@oss.qualcomm.com> Content-Language: en-US From: Jie Luo In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI5MDEwOSBTYWx0ZWRfXzp/Kt5mzRz5L +1lFnRULu5MjfJmwmUZB01rkjaFbZiTdAvlZA75yIaa1A9yXabS7XgtSScks0AQxv441390SMk4 1/JSrik5vSOYq30ZAdl++x2BaMzg2pyYKkE+6jBrLwIorFDZiNXN5TaRkZ8TZj176qFudvhNzME raNvVyER3KQoI8em3LL3QrtejzHCvnOMEB8pp0aP7/P4UytgvSVVPMU9YMRabtqU5sgZ7WQgzOI DyCNLplQrvPA1HPK/Pt7JY1nqUt7syGJLIoBEvye5SP2BVbESTbx2NA9xrtihuxBf2PcSKXl1py 1/uwOoG1LRZV8svs1E8VkPYmUZMHG9DWV4OJNdn3NKKuB3Azq3eNm4wqeke3DBesojcn0UqDogt vn9T+pyZ1UFqLZw04MsEVMiY0BHaACRN/snjsXulZgDYmjXAKasoL71zaL5pnBZYf5ZQb5XR3SH /3aBg7bGEbRyx2vQ92g== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI5MDEwOSBTYWx0ZWRfX+hVezD548h/I eIHZEhtjPDucFDt6hWb+n1fBY/MVjwj9k/6URtRuIu7dhupjR6xI8hVH8h3pRLevsoWAsYo4qLG z9hSdOE8KNDUqzjVCoDBNhFFxaM/EQ8= X-Proofpoint-ORIG-GUID: 6tkBchwmq1-UHrZ3sY16sE71XtH4BA1o X-Proofpoint-GUID: 6tkBchwmq1-UHrZ3sY16sE71XtH4BA1o X-Authority-Analysis: v=2.4 cv=EsriaycA c=1 sm=1 tr=0 ts=6a69fd06 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=mo-5zohwMfGRhBBTFyAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-29_05,2026-07-28_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607290109 On 7/28/2026 5:29 PM, Konrad Dybcio wrote: > On 7/24/26 5:00 PM, Luo Jie wrote: >> The NSS (network subsystem) clock is derived from the CMN PLL output >> divided by 2 and then further divided by a configurable 6-bit divider >> with a valid range of 8-63. >> >> Signed-off-by: Luo Jie >> --- > > This looks very similar to clk-regmap-divider.c (or at least to > the generic clk-divider.c implementation). > You're right — this can be converted to use clk_regmap_div_ops directly. The NSS and PPE clocks both compute rate = parent_rate / (2 * div), where div is read/written straight from a register field with no other transform. The only thing blocking reuse of clk_regmap_div_ops is that implicit 2 *, which none of the existing CLK_DIVIDER_* flags express. I'll add a new flag CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET, to clk- divider.c/clk-provider.h to express that relationship, pass a flags field through struct clk_regmap_div (clk-regmap-divider.c/.h) so qcom clock drivers can opt into it, and register both NSS and PPE as plain clk_regmap_div instances with .ops = &clk_regmap_div_ops instead of hand-rolling recalc_rate/set_rate. > [...] > >> /* Register the fixed rate output clocks. */ >> for (i = 0; i < num_clks; i++) { >> - struct clk_parent_data pdata = { .hw = cmn_pll_hw }; >> + if (fixed_clk[i].rate) { >> + struct clk_parent_data pdata = { .hw = cmn_pll_hw }; >> + >> + hw = devm_clk_hw_register_fixed_rate_parent_data(dev, >> + fixed_clk[i].name, >> + &pdata, 0, >> + fixed_clk[i].rate); >> + } else if (!strcmp(fixed_clk[i].name, "nss")) { >> + hw = ipq_cmn_pll_nss_register(pdev, cmn_pll->regmap, >> + cmn_pll_hw); > > Huge "no", this must be a compile-time constant and not rely on > some funky detection. > > Konrad Thanks. Will replace the rate/enable_bit/strcmp(name, ...) runtime inference with an explicit enum cmn_pll_clk_type field, set directly by each entry's construction macro (CLK_PLL_OUTPUT/CLK_PLL_GATE/ CLK_PLL_NSS/CLK_PLL_PPE/CLK_PLL_PON/CLK_PLL_EPHY_RAW), and dispatch via switch in ipq_cmn_pll_register_clks().