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Thu, 15 Oct 2026 00:15:34 -0700 (PDT) X-Received: by 2002:a17:90b:3a48:b0:3a0:9640:803a with SMTP id 98e67ed59e1d1-3ab3a33db41mr16430141a91.5.1792048533687; Thu, 15 Oct 2026 00:15:33 -0700 (PDT) Received: from [10.217.216.28] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ac92a43d98sm1617534a91.0.2026.10.15.00.15.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Oct 2026 00:15:33 -0700 (PDT) Message-ID: Date: Thu, 15 Oct 2026 12:45:23 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] dt-bindings: clock: qcom: Add bindings for PDM GP_MN clock divider To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Richard Cochran , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org References: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> <20260602-pdm_clk_gp_mnd_v1-v1-1-1522662b6c53@oss.qualcomm.com> <03ec182f-b1a2-4ebe-8e48-9e88168f7694@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <03ec182f-b1a2-4ebe-8e48-9e88168f7694@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: i9zeKMxRO_1T9gGe4nUIE2PcKOBq4cqm X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE1MDAyOCBTYWx0ZWRfX5LGkzl+ioVYu CThQ70yQcWM5Q/RpOt3Gxfgvd0xVAuf2HQpSzlK8qba9a2sDLFInW80CfMcaUPrCzcxTZZ+P0yz PJEiV3FApdcPc14runyotXzbszc00tc= X-Proofpoint-GUID: i9zeKMxRO_1T9gGe4nUIE2PcKOBq4cqm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE1MDAyOCBTYWx0ZWRfXxhs/9TOYMSAN AG0xwRSBp6X8s1OhTwbufUyYrdYxio7IbnbTALl8eeKVey/RlR5r+M3NKjk5KVSDc+tFkseaXIK MBkNk29p36qlOMMC2oI+5n4KQXvkuUgKqHoGzWEwdfA7jwYZNguIG8UKk1D7arZLoeEk+GqXoI1 rNHQhKShPSL3bDpzqUtVObhPZt1sFgBhshIajmcMMcVVvUhJeff5wWUQPdJX295WSbYFctYdY85 qF/WwAFRUweqZEFY2YKLOgImbD2PtAo3rGg8Rw8fsRisAhMSAug0pPLxByfz11BmvW1D5EyYceN UzOK2f9F/BflGEWAtCuCo/vEoCiHN6vJmyCX/ZkA5cFVLO/w7Qk7LdefJmPntGQpdy74Mss7IUW Ky0Q+HQN+vs1gBGykLqBRgg+CZLZXSt6F4KsGEKomvT9X4VDicOtahrjEjYIBvpwrXH+g4UVxkW QGc1nCGginCH2AQu3Hw== X-Authority-Analysis: v=2.4 cv=SYZi5fRu c=1 sm=1 tr=0 ts=6ad07d96 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=PM9MLdjoRCq9o7e-zGMA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610150028 On 6/9/2026 6:55 PM, Konrad Dybcio wrote: > On 6/2/26 5:21 PM, Taniya Das wrote: >> Add device tree bindings for the Qualcomm Peripheral Web's PDM GP_MN >> clock divider. The hardware generates a fractional output frequency >> from a fixed input clock (typically TCXO4) using the relation >> Fout = Fin * (M / N), with duty cycle controlled by a separate D >> register. The clock output is routed over a gpio controlled pin. >> >> Signed-off-by: Taniya Das >> --- > > [...] >> + clock-output-names: >> + maxItems: 1 > > This should be deferred to the driver Sure. > >> + >> + pinctrl-0: >> + description: Pin configuration for the GP_MN output in the active state. >> + >> + pinctrl-names: >> + items: >> + - const: active > > I think these 2 are always allowed/defined Sure, will remove them. >> + >> + assigned-clocks: >> + maxItems: 1 >> + description: Parent clock phandle used to set the input frequency. >> + >> + assigned-clock-rates: >> + maxItems: 1 >> + description: | >> + Rate for the parent clock in Hz. >> + Supported rates: 19200000, 9600000, 6400000, 4800000. > > Likewise, we could simply set_rate on the GCC clock which is the > parent of this one, via something like CLK_SET_RATE_PARENT The GCC clock could be either at 19.2MHz, 9.6MHz, 6.4MHz, or 4.8MHz(consumer/customer use case dependent) and the output clock at GP_MND can be a range of frequencies(which are not fixed). assigned-clock-rates | v bi_tcxo (19.2 MHz) | v CDIV (1, 2, 3, 4) | | v gcc_pdm_xo4_clk (CBC) | +----> 19.2 MHz +----> 9.6 MHz +----> 6.4 MHz +----> 4.8 MHz | v PDM GP_MND (Variable frequency range) I missed one patch where I didn't add the CLK_SET_RATE_PARENT on the gcc_pdm_xo4_clk and CDIV(additional) modelling. -- Thanks, Taniya Das