From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 634D935A384 for ; Sat, 25 Jul 2026 02:59:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784948377; cv=none; b=VAKaeUibJQYbsHGN4ZsMLOoKTIVCvOdGzxuDlzq4WG5DrAE0bcMb6SOxeGAAlsOefI7n74ewCews2qS/rp7sE/TDtr8mBw06p0Q2TGliFWb4lksDIZrcliS5XyOyDBgmXrOzEg55y7JOiuitkMTu4gF+QZeRdNIJDylT5rby4sA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784948377; c=relaxed/simple; bh=yaFXhpBnBAIgzpCNFMP9nZFJIf27fX86MplXilh5Kyo=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ml5ma+21rbxdN7Mo3KbkxA5iWrFznKN5x2qBpmG65e7rqDavUKLC+dVaqad7FVlG1Ajcf+rKMTlS/Bl+zY7aW80Hucj+YFwux3DfpZF29wXdlVLqwKe+c1eIZd72ycb4tQXP6C4yd7c0WAoDif0wx/1SDpgOe9EFDKVcZ/rEqKo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1wnSbp-0000000032V-3ApD; Sat, 25 Jul 2026 02:59:29 +0000 Date: Sat, 25 Jul 2026 03:59:26 +0100 From: Daniel Golle To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Allen Chen , Hermes Wu , Pin-yen Lin , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Chen-Yu Tsai Subject: [PATCH v6 06/13] drm/bridge: it6505: avoid division by zero in pixel clock calculation Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: it6505_calc_video_info() checks the sum of the three pixel clock counter samples for zero before dividing it by 3, so sums of 1 or 2 truncate to 0 and the following pixel clock calculation divides by zero. Divide first and check the result. Fixes: b5c84a9edcd4 ("drm/bridge: add it6505 driver") Signed-off-by: Daniel Golle --- v6: no changes v5: new patch drivers/gpu/drm/bridge/ite-it6505.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c index 3806b0b96637..b7eb746c8f8e 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -751,12 +751,13 @@ static void it6505_calc_video_info(struct it6505 *it6505) sum += rddata; } + sum /= 3; + if (sum == 0) { DRM_DEV_DEBUG_DRIVER(dev, "calc video timing error"); return; } - sum /= 3; pclk = 13500 * 2048 / sum; it6505->video_info.clock = pclk; it6505->video_info.hdisplay = hdew; -- 2.55.0