From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35ABFC38142 for ; Tue, 31 Jan 2023 07:53:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230481AbjAaHxd (ORCPT ); Tue, 31 Jan 2023 02:53:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230273AbjAaHxb (ORCPT ); Tue, 31 Jan 2023 02:53:31 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60FFA28D04 for ; Mon, 30 Jan 2023 23:53:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675151605; x=1706687605; h=message-id:date:mime-version:cc:subject:to:references: from:in-reply-to:content-transfer-encoding; bh=JG+wb8bqGbnOoAJrhM94NIsc3fCfzpe0Naap9WNrSdA=; b=a3PpqgyvMq9G17Ubn2KjixXgzmHYGX0lLxO+esRvDqvx3ujmW0hRjxSj w1COvtaCGr4N+gJICCOinKKehdDNvtn3lJBTI+7tZnCtlwieilk/FkaQm YrD9rtH+HRXXjkwassHQ73qIi0QqtvE9Jb0Sb9Q1/Lsob6I6vwkIazOU2 44TrCbRMVEpYcxbJise+5vyAh0bwkWLSSLULC2h6aZDepEuUXY59XAdjY d7bD/r3D5kxMvJroPN74TrbyeH3hU1tHel/q23WYUZNDDBStaxCkTx/tb ei8Mqk2WrSQpf+7sqil/oQ8XTHsZAIcNUT8IKKmhwYgm7DHV73ClKTL0k g==; X-IronPort-AV: E=McAfee;i="6500,9779,10606"; a="307434054" X-IronPort-AV: E=Sophos;i="5.97,259,1669104000"; d="scan'208";a="307434054" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2023 23:53:25 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10606"; a="666392693" X-IronPort-AV: E=Sophos;i="5.97,259,1669104000"; d="scan'208";a="666392693" Received: from blu2-mobl.ccr.corp.intel.com (HELO [10.249.172.41]) ([10.249.172.41]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2023 23:53:23 -0800 Message-ID: Date: Tue, 31 Jan 2023 15:53:20 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Cc: baolu.lu@linux.intel.com, Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Ashok Raj , linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/1] iommu/vt-d: Set No Execute Enable bit in PASID table entry Content-Language: en-US To: iommu@lists.linux.dev References: <20230126095438.354205-1-baolu.lu@linux.intel.com> From: Baolu Lu In-Reply-To: <20230126095438.354205-1-baolu.lu@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2023/1/26 17:54, Lu Baolu wrote: > Setup No Execute Enable bit (Bit 133) of a scalable mode PASID > entry. It is required when XD bit of the first level page table > entry is about to be set. > > Fixes: ddf09b6d43ec ("iommu/vt-d: Setup pasid entries for iova over first level") > Signed-off-by: Ashok Raj > Signed-off-by: Lu Baolu Patch queued for v6.3. https://lore.kernel.org/linux-iommu/20230131073740.378984-1-baolu.lu@linux.intel.com/ Best regards, baolu