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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5c00309a58bsm497564e87.73.2026.11.06.13.24.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Nov 2026 13:24:25 -0800 (PST) Message-ID: Date: Fri, 6 Nov 2026 23:24:24 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/7] dt-bindings: phy: qcom,sm8150-csi2-phy: Add SM8150 CSI2 PHY To: mail@andrewgigena.dev, Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Mauro Carvalho Chehab , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Andi Shyti , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org References: <20261106-sm8150-v7.4-rc1-camss-v3-0-0103e8a0bbcd@andrewgigena.dev> <20261106-sm8150-v7.4-rc1-camss-v3-3-0103e8a0bbcd@andrewgigena.dev> From: Vladimir Zapolskiy In-Reply-To: <20261106-sm8150-v7.4-rc1-camss-v3-3-0103e8a0bbcd@andrewgigena.dev> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Andrew, On 11/6/26 20:35, Andrew Gigena via B4 Relay wrote: > From: Andrew Gigena > > Document the Qualcomm SM8150 MIPI CSI2 D-PHY. The PHY sits between the > CSI2 sensor and the CAMSS CSI decoder and is fed by the CSIPHY "core" and > "timer" clocks, the TITAN top power domain and the vdda-phy/vdda-pll > supplies. > > Unlike the X1E80100 C-PHY/D-PHY combo PHY, SM8150 only has a D-PHY, has > no separate AHB clock and no MMCX/MX power domains, so describe it in a > dedicated schema. > very much appreciated for changing the CAMSS phys to this format. Please double check if SM8150 CSIPHY v1.1 is capable of C-PHY: * https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/LA.UM.8.1.r1-16600-sm8150.0/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c#L239-256 D-PHY combo mode is also supported on the CSIPHY apparently. Likely these features are supported on SM8150. > Signed-off-by: Andrew Gigena > --- > .../bindings/phy/qcom,sm8150-csi2-phy.yaml | 163 +++++++++++++++++++++ > 1 file changed, 163 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sm8150-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sm8150-csi2-phy.yaml > new file mode 100644 > index 000000000000..86d8970d1119 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,sm8150-csi2-phy.yaml > @@ -0,0 +1,163 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,sm8150-csi2-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8150 SoC CSI2 PHY > + > +maintainers: > + - Andrew Gigena > + > +description: > + Qualcomm MIPI CSI2 D-PHY. Connects MIPI CSI2 sensors to Qualcomm's Camera > + CSI decoder (CAMSS). > + > +properties: > + compatible: > + const: qcom,sm8150-csi2-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: core > + - const: timer > + > + interrupts: > + maxItems: 1 > + > + operating-points-v2: true > + > + opp-table: > + type: object > + > + power-domains: > + maxItems: 1 > + > + power-domain-names: > + items: > + - const: top In downstream camcc-sm8150.c, PLL0 is on MX, and PLL0 supplies CSIPHY clocks. I believe MX shall be added to the list of 'power-domains'. > + > + vdda-phy-supply: > + description: Phandle to a 0.88V regulator supply to a PHY. > + > + vdda-pll-supply: > + description: Phandle to a 1.2V regulator supply to a PHY PLL. Still it would be preferred to get 'vdda-0p9-supply' and 'vdda-1p2-supply' properties. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Sensor input. A single sensor is described by a single endpoint with > + one to four data lanes, numbered 1-4. The clock lane is position 0. > + > + properties: > + endpoint: Back to downstream * https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/LA.UM.8.1.r1-16600-sm8150.0/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c#L239-256 D-PHY combo mode is also supported on the SM8150 CSIPHY apparently, it shall be reflected in a way that two endpoints could be present. > + $ref: /schemas/media/video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + bus-type: > + enum: > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY > + default: 4 Please double check if SM8150 CSIPHY v1.1 is capable of C-PHY: * https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/LA.UM.8.1.r1-16600-sm8150.0/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c#L239-256 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + items: > + minimum: 1 > + maximum: 4 > + > + required: > + - data-lanes > + - remote-endpoint > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Output to the CAMSS CSI input port. > + > + required: > + - port@0 > + - port@1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - operating-points-v2 > + - power-domains > + - power-domain-names > + - vdda-phy-supply > + - vdda-pll-supply > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + phy@ac65000 { > + compatible = "qcom,sm8150-csi2-phy"; > + reg = <0xac65000 0x1000>; > + > + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; > + clock-names = "core", > + "timer"; > + > + interrupts = ; > + > + operating-points-v2 = <&csiphy0_opp_table>; > + > + power-domains = <&camcc TITAN_TOP_GDSC>; > + power-domain-names = "top"; > + > + vdda-phy-supply = <&vreg_l5a_0p88>; > + vdda-pll-supply = <&vreg_l12a_1p2>; > + > + csiphy0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + }; > + }; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + endpoint { > + bus-type = ; > + data-lanes = <1 2 3 4>; > + remote-endpoint = <&sensor_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + endpoint { > + remote-endpoint = <&camss_csi0_in>; > + }; > + }; > + }; > + }; > In general the change looks good, thank you, but likely it can be embedded into the scheme for X1E. -- Best wishes, Vladimir