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bits=128/128); Thu, 17 Sep 2026 09:08:21 -0700 (PDT) Message-ID: Date: Thu, 17 Sep 2026 17:08:20 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 2/2] clk: qcom: Add LPASS VA CSR heartbeat pulse clock To: sarath.ganapathiraju@oss.qualcomm.com, andersson@kernel.org, abelvesa@kernel.org, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, prasad.kumpatla@oss.qualcomm.com References: <20260917-master-v8-0-823d2c5d090a@oss.qualcomm.com> <20260917-master-v8-2-823d2c5d090a@oss.qualcomm.com> Content-Language: en-US From: Srinivas Kandagatla In-Reply-To: <20260917-master-v8-2-823d2c5d090a@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: W_0JWGtNBjEp9b1Z8vl8a49uZuexlG8f X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE3MDIyOCBTYWx0ZWRfX4UK1pLXmlU7y ZsKvv3KUNY3xdswGDIG7qhaKhBiC/iC/PY1ngUNSfLYxj5WU/PUQp4mv/gKumyMp4cPULwbH6uY YRvQdUMSBa6M3IJ3UcKmVlE3VTHdvzW5K48/uOtxtKATMYouyMIcoq52K6oeExUpHy7l4LcYlns hWmQ2o6vxm3MB5AGIT6GVmFAA+sE5hkVVmPsmhWh7/5CHLvc3rNuDvj7ThSCP8a1qBuqDMF37Yb h3NRbv8pNSJJgoJpPI99a55us9SONh2gfpVN0XZc2hUpnW+ah7PmChCmi8gw9YdQk83ZiP3kMqn fYyMf3dyZ+o83rWpJWaoe1+ogjIZfetYMQcg7YbwUgh+wQQiwCqHQwf5aIQPYF6Ce5ptbZnyiie Q3USNwVqv/NlUsAmAnWjtVsLXE27/CQaeHXHf/IFNiDR1Ph2HwfppsVVGxCnHEKeyb9t6RqtTrY 6LIK0+m/FULCOI3LEPA== X-Proofpoint-GUID: W_0JWGtNBjEp9b1Z8vl8a49uZuexlG8f X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE3MDIyOCBTYWx0ZWRfX71eVPbl7hlGv sNcuctVP2LU4rh9zmbF+0V33lofspxJqw5aNrqcCqSRlc+dy7QLpLrqxmW2/of9Gy6dHSNucL2T 9+ScugIIcBK7Bf03QXHhzoF9l3vF3+o= X-Authority-Analysis: v=2.4 cv=dMUzC+Zb c=1 sm=1 tr=0 ts=6aac1077 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=ZsC4DHZuhs/kKio7QBcDoQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=Kn2qpGTL2itX_U7O_l0A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-17_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 suspectscore=0 spamscore=0 phishscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609170228 On 9/17/26 2:57 PM, Sarath Ganapathiraju via B4 Relay wrote: > From: Sarath Ganapathiraju > > The HeartBeat Pulse, also known as RateGen Pulse, synchronizes the > start of DMAs and Codec Interfaces for the audio usecases and can > serve as a periodic wakeup source for the DSP. > > Add the LPASS VA CSR driver that models the rate generator as a clock > provider so it is enabled and disabled automatically alongside the > other clocks during runtime PM resume and suspend. > > Attach the DT vote clocks to runtime PM and resume the device before > programming the rate generator registers, so register accesses happen > only after the LPASS votes are active. > > Signed-off-by: Sarath Ganapathiraju Lgtm, Reviewed-by: Srinivas Kandagatla --srini > --- > drivers/clk/qcom/Kconfig | 14 ++++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/lpass-va-csr.c | 140 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 155 insertions(+) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 6ef083f5d9e2..32172f2dfe3c 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -2116,6 +2116,20 @@ config CLK_GFM_LPASS_SM8250 > Support for the Glitch Free Mux (GFM) Low power audio > subsystem (LPASS) clocks found on SM8250 SoCs. > > +config QCOM_CLK_LPASS_HEARTBEAT_PULSE > + tristate "Qualcomm LPASS VA CSR heartbeat pulse clock provider" > + depends on COMMON_CLK > + depends on ARM64 || COMPILE_TEST > + select REGMAP_MMIO > + default m if ARCH_QCOM > + help > + Qualcomm LPASS VA CSR block contains the rate generator hardware > + that produces the HeartBeat Pulse (also known as RateGen Pulse). > + This driver models the rate generator as a clock provider so > + that consumers can enable or disable it via the common clock > + framework, and it can be used to synchronize the start of DMAs > + and Codec Interfaces or as a periodic wakeup source for the DSP. > + > config SM_VIDEOCC_8450 > tristate "SM8450 Video Clock Controller" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index a6c676f68b79..66c8501c21a3 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_ELIZA_GPUCC) += gpucc-eliza.o > obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o > obj-$(CONFIG_CLK_ELIZA_VIDEOCC) += videocc-eliza.o > obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o > +obj-$(CONFIG_QCOM_CLK_LPASS_HEARTBEAT_PULSE) += lpass-va-csr.o > obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o > obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o > obj-$(CONFIG_CLK_GLYMUR_EVACC) += evacc-glymur.o > diff --git a/drivers/clk/qcom/lpass-va-csr.c b/drivers/clk/qcom/lpass-va-csr.c > new file mode 100644 > index 000000000000..3c87c3319f15 > --- /dev/null > +++ b/drivers/clk/qcom/lpass-va-csr.c > @@ -0,0 +1,140 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "clk-branch.h" > +#include "clk-regmap.h" > + > +#define LPASS_RATE_GEN_CTRL 0xd000 > +#define LPASS_RATE_GEN_COUNTER_0 0xd004 > +#define LPASS_RATE_GEN_DELAY 0xd010 > + > +#define LPASS_RATE_GEN_MAX_REG LPASS_RATE_GEN_DELAY > + > +#define LPASS_RG_CTRL_EN BIT(0) > + > +struct lpass_va_csr_data { > + u32 counter_0; > + u32 delay; > +}; > + > +static const struct lpass_va_csr_data hawi_csr_data = { > + .counter_0 = 0x960, > + .delay = 0x16, > +}; > + > +static const struct regmap_config lpass_rate_gen_regmap_config = { > + .name = "lpass_rate_gen", > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > + .max_register = LPASS_RATE_GEN_MAX_REG, > + .cache_type = REGCACHE_MAPLE, > +}; > + > +struct lpass_va_csr { > + struct clk_regmap hb; > +}; > + > +static int lpass_va_csr_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + const struct lpass_va_csr_data *data = of_device_get_match_data(dev); > + struct lpass_va_csr *csr; > + struct clk_init_data init = { > + .name = "lpass_heartbeat_pulse", > + .ops = &clk_branch_simple_ops, > + }; > + struct regmap *regmap; > + void __iomem *base; > + int ret; > + > + csr = devm_kzalloc(dev, sizeof(*csr), GFP_KERNEL); > + if (!csr) > + return -ENOMEM; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + regmap = devm_regmap_init_mmio(dev, base, > + &lpass_rate_gen_regmap_config); > + if (IS_ERR(regmap)) > + return dev_err_probe(dev, PTR_ERR(regmap), > + "failed to init regmap\n"); > + > + ret = devm_pm_runtime_enable(dev); > + if (ret) > + return dev_err_probe(dev, ret, "failed to enable PM runtime\n"); > + > + ret = devm_pm_clk_create(dev); > + if (ret) > + return ret; > + > + ret = of_pm_clk_add_clks(dev); > + if (ret < 0) > + return dev_err_probe(dev, ret, "failed to get vote clocks\n"); > + > + ret = pm_runtime_resume_and_get(dev); > + if (ret) > + return ret; > + > + ret = regmap_write(regmap, LPASS_RATE_GEN_COUNTER_0, data->counter_0); > + if (ret) > + goto err_pm_runtime_put; > + > + ret = regmap_write(regmap, LPASS_RATE_GEN_DELAY, data->delay); > + if (ret) > + goto err_pm_runtime_put; > + > + csr->hb.regmap = regmap; > + csr->hb.enable_reg = LPASS_RATE_GEN_CTRL; > + csr->hb.enable_mask = LPASS_RG_CTRL_EN; > + csr->hb.hw.init = &init; > + > + ret = devm_clk_register_regmap(dev, &csr->hb); > + if (ret) > + goto err_pm_runtime_put; > + > + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &csr->hb.hw); > + if (ret) > + goto err_pm_runtime_put; > + > + pm_runtime_put(dev); > + > + return 0; > + > +err_pm_runtime_put: > + pm_runtime_put(dev); > + > + return ret; > +} > + > +static const struct of_device_id lpass_va_csr_dt_match[] = { > + { .compatible = "qcom,hawi-lpass-va-csr", .data = &hawi_csr_data }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, lpass_va_csr_dt_match); > + > +static struct platform_driver lpass_va_csr_driver = { > + .driver = { > + .name = "qcom-lpass-va-csr", > + .of_match_table = lpass_va_csr_dt_match, > + }, > + .probe = lpass_va_csr_probe, > +}; > + > +module_platform_driver(lpass_va_csr_driver); > + > +MODULE_DESCRIPTION("Qualcomm LPASS VA CSR heartbeat pulse clock provider"); > +MODULE_LICENSE("GPL"); >