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Fri, 05 Dec 2025 17:29:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IG4ghndnLUTwdPbWBg93PiHhWZqYjSRpjlaaHQl1YIklJbUj/BDHblAINfPMFltLyT7dRC5wA== X-Received: by 2002:a05:6a00:2303:b0:7e8:3fcb:bc44 with SMTP id d2e1a72fcca58-7e8bb06ee59mr1098679b3a.25.1764984575442; Fri, 05 Dec 2025 17:29:35 -0800 (PST) Received: from [192.168.29.63] ([49.43.226.9]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7e2adc5c355sm6308508b3a.33.2025.12.05.17.29.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Dec 2025 17:29:35 -0800 (PST) Message-ID: Date: Sat, 6 Dec 2025 06:59:28 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] PCI: rzg3s-host: Use pci_generic_config_write() for the root bus To: Claudiu , bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Bjorn Helgaas References: <20251205112443.1408518-1-claudiu.beznea.uj@bp.renesas.com> <20251205112443.1408518-2-claudiu.beznea.uj@bp.renesas.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20251205112443.1408518-2-claudiu.beznea.uj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Xpi4rWtKb5vrcXRzp4kaJfE8YoJRaXBf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA2MDAwOSBTYWx0ZWRfX5ktx7XCBXX4p KWVf9tRhTacJq0rTPleG3dIF6wPCy1kNVjbsaS6H69FurT2GZpCP2N9vZrO5CDVx4962tMNs18J vwndQqxLOO3blzNW4CNtIkiU0saRrtNY3mR4mBc+m7/cPU9FpMLyv7A4dqynusSAsYSvHTc5bMx WefI/xiGng55Dstql5tJ9lu6tmxL94Bu3Kr17INwjjaobH74L3yeCJsnuVzByZwjA9oKfbq+tvw lr30nuC7ygIJO/OFGfIZ7UnkPbMQal0694XBT0hU5NWz/RShJYEt2ErADmWXrPzN3J3KMmjnb0h FiAuzzwN7Kquungz55S3ZJ0irhybbf6IMEsM/wgxIHnbUEsisa6B0AY00i63M8NsNEsUFuqwMi1 ifIKA8bwrcoAgBUAg/9PdkBV0pC8vQ== X-Proofpoint-ORIG-GUID: Xpi4rWtKb5vrcXRzp4kaJfE8YoJRaXBf X-Authority-Analysis: v=2.4 cv=NsHcssdJ c=1 sm=1 tr=0 ts=69338701 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=gtzuW6mAKwlXd79hODmrug==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=yC-0_ovQAAAA:8 a=VwQbUJbxAAAA:8 a=LsleVm4LR1ejaCuuDOAA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-05_09,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 clxscore=1015 phishscore=0 priorityscore=1501 malwarescore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512060009 On 12/5/2025 4:54 PM, Claudiu wrote: > From: Claudiu Beznea > > The Renesas RZ/G3S host controller allows writing to read-only PCIe > configuration registers when the RZG3S_PCI_PERM_CFG_HWINIT_EN bit is set in > the RZG3S_PCI_PERM register. However, callers of struct pci_ops::write > expect the semantics defined by the PCIe specification, meaning that writes > to read-only registers must not be allowed. > > The previous custom struct pci_ops::write implementation for the root bus > temporarily enabled write access before calling pci_generic_config_write(). > This breaks the expected semantics. > > Remove the custom implementation and simply use pci_generic_config_write(). > > Along with this change, the updates of the PCI_PRIMARY_BUS, > PCI_SECONDARY_BUS, and PCI_SUBORDINATE_BUS registers were moved so that > they no longer depends on the RZG3S_PCI_PERM_CFG_HWINIT_EN bit in the > RZG3S_PCI_PERM_CFG register, since these registers are R/W. > Don't you need fixes tag and back port to stable kernels, this patch looks like a bug fix. - Krishna Chaitanya. > Suggested-by: Bjorn Helgaas > Signed-off-by: Claudiu Beznea > --- > drivers/pci/controller/pcie-rzg3s-host.c | 27 ++++-------------------- > 1 file changed, 4 insertions(+), 23 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c > index 667e6d629474..547cbe676a25 100644 > --- a/drivers/pci/controller/pcie-rzg3s-host.c > +++ b/drivers/pci/controller/pcie-rzg3s-host.c > @@ -439,28 +439,9 @@ static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus, > return host->pcie + where; > } > > -/* Serialized by 'pci_lock' */ > -static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn, > - int where, int size, u32 val) > -{ > - struct rzg3s_pcie_host *host = bus->sysdata; > - int ret; > - > - /* Enable access control to the CFGU */ > - writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN, > - host->axi + RZG3S_PCI_PERM); > - > - ret = pci_generic_config_write(bus, devfn, where, size, val); > - > - /* Disable access control to the CFGU */ > - writel_relaxed(0, host->axi + RZG3S_PCI_PERM); > - > - return ret; > -} > - > static struct pci_ops rzg3s_pcie_root_ops = { > .read = pci_generic_config_read, > - .write = rzg3s_pcie_root_write, > + .write = pci_generic_config_write, > .map_bus = rzg3s_pcie_root_map_bus, > }; > > @@ -1065,14 +1046,14 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host) > writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L); > writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U); > > + /* Disable access control to the CFGU */ > + writel_relaxed(0, host->axi + RZG3S_PCI_PERM); > + > /* Update bus info */ > writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS); > writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS); > writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS); > > - /* Disable access control to the CFGU */ > - writel_relaxed(0, host->axi + RZG3S_PCI_PERM); > - > return 0; > } >