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Mon, 09 Dec 2024 12:28:20 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B9CSJ5D012083 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Dec 2024 12:28:19 GMT Received: from [10.216.3.14] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Dec 2024 04:28:13 -0800 Message-ID: Date: Mon, 9 Dec 2024 17:58:10 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/7] drm/msm: adreno: find bandwidth index of OPP and set it along freq index To: Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , "Dmitry Baryshkov" , Marijn Suijten , David Airlie , "Simona Vetter" , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , References: <20241205-topic-sm8x50-gpu-bw-vote-v4-0-9650d15dd435@linaro.org> <20241205-topic-sm8x50-gpu-bw-vote-v4-4-9650d15dd435@linaro.org> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <20241205-topic-sm8x50-gpu-bw-vote-v4-4-9650d15dd435@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ADqLIW4KrKPSheXYj7AW-Ab5JJuP82K4 X-Proofpoint-GUID: ADqLIW4KrKPSheXYj7AW-Ab5JJuP82K4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 malwarescore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412090098 On 12/5/2024 8:31 PM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale the DDR Bandwidth > along the Frequency and Power Domain level, until now we left the OPP > core scale the OPP bandwidth via the interconnect path. > > In order to enable bandwidth voting via the GPU Management > Unit (GMU), when an opp is set by devfreq we also look for > the corresponding bandwidth index in the previously generated > bw_table and pass this value along the frequency index to the GMU. > > The GMU also takes another vote called AB which is a 16bit quantized > value of the floor bandwidth against the maximum supported bandwidth. > > The AB is calculated with a default 25% of the bandwidth like the > downstream implementation too inform the GMU firmware the minimal > quantity of bandwidth we require for this OPP. > > Since we now vote for all resources via the GMU, setting the OPP > is no more needed, so we can completely skip calling > dev_pm_opp_set_opp() in this situation. > > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Neil Armstrong Reviewed-by: Akhil P Oommen -Akhil > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 39 +++++++++++++++++++++++++++++++++-- > drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 +- > drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 6 +++--- > drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 5 +++++ > 4 files changed, 46 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 36696d372a42a27b26a018b19e73bc6d8a4a5235..46ae0ec7a16a41d55755ce04fb32404cdba087be 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -110,9 +110,11 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, > bool suspended) > { > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + const struct a6xx_info *info = adreno_gpu->info->a6xx; > struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > struct a6xx_gmu *gmu = &a6xx_gpu->gmu; > u32 perf_index; > + u32 bw_index = 0; > unsigned long gpu_freq; > int ret = 0; > > @@ -125,6 +127,37 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, > if (gpu_freq == gmu->gpu_freqs[perf_index]) > break; > > + /* If enabled, find the corresponding DDR bandwidth index */ > + if (info->bcms && gmu->nr_gpu_bws > 1) { > + unsigned int bw = dev_pm_opp_get_bw(opp, true, 0); > + > + for (bw_index = 0; bw_index < gmu->nr_gpu_bws - 1; bw_index++) { > + if (bw == gmu->gpu_bw_table[bw_index]) > + break; > + } > + > + /* Vote AB as a fraction of the max bandwidth */ > + if (bw) { > + u64 tmp; > + > + /* For now, vote for 25% of the bandwidth */ > + tmp = bw * 25; > + do_div(tmp, 100); > + > + /* > + * The AB vote consists of a 16 bit wide quantized level > + * against the maximum supported bandwidth. > + * Quantization can be calculated as below: > + * vote = (bandwidth * 2^16) / max bandwidth > + */ > + tmp *= MAX_AB_VOTE; > + do_div(tmp, gmu->gpu_bw_table[gmu->nr_gpu_bws - 1]); > + > + bw_index |= AB_VOTE(clamp(tmp, 1, MAX_AB_VOTE)); > + bw_index |= AB_VOTE_ENABLE; > + } > + } > + > gmu->current_perf_index = perf_index; > gmu->freq = gmu->gpu_freqs[perf_index]; > > @@ -140,8 +173,10 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, > return; > > if (!gmu->legacy) { > - a6xx_hfi_set_freq(gmu, perf_index); > - dev_pm_opp_set_opp(&gpu->pdev->dev, opp); > + a6xx_hfi_set_freq(gmu, perf_index, bw_index); > + /* With Bandwidth voting, we now vote for all resources, so skip OPP set */ > + if (!bw_index) > + dev_pm_opp_set_opp(&gpu->pdev->dev, opp); > return; > } > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > index 2062a2be224768c1937d7768f7b8439920e9e127..0c888b326cfb485400118f3601fa5f1949b03374 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > @@ -209,7 +209,7 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu); > int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state); > void a6xx_hfi_stop(struct a6xx_gmu *gmu); > int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu); > -int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index); > +int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, u32 perf_index, u32 bw_index); > > bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); > bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > index fc4bfad51de9a3b6617fbbd03471a5851d43ce88..5c566ce6612ed25763337d20de90d78697dfb801 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > @@ -765,13 +765,13 @@ static int a6xx_hfi_send_core_fw_start(struct a6xx_gmu *gmu) > sizeof(msg), NULL, 0); > } > > -int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index) > +int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, u32 freq_index, u32 bw_index) > { > struct a6xx_hfi_gx_bw_perf_vote_cmd msg = { 0 }; > > msg.ack_type = 1; /* blocking */ > - msg.freq = index; > - msg.bw = 0; /* TODO: bus scaling */ > + msg.freq = freq_index; > + msg.bw = bw_index; > > return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_GX_BW_PERF_VOTE, &msg, > sizeof(msg), NULL, 0); > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h > index 528110169398f69f16443a29a1594d19c36fb595..52ba4a07d7b9a709289acd244a751ace9bdaab5d 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h > @@ -173,6 +173,11 @@ struct a6xx_hfi_gx_bw_perf_vote_cmd { > u32 bw; > }; > > +#define AB_VOTE_MASK GENMASK(31, 16) > +#define MAX_AB_VOTE (FIELD_MAX(AB_VOTE_MASK) - 1) > +#define AB_VOTE(vote) FIELD_PREP(AB_VOTE_MASK, (vote)) > +#define AB_VOTE_ENABLE BIT(8) > + > #define HFI_H2F_MSG_PREPARE_SLUMBER 33 > > struct a6xx_hfi_prep_slumber_cmd { >