From: Trilok Soni <trilokkumar.soni@oss.qualcomm.com>
To: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>,
Jens Wiklander <jenswi@kernel.org>,
Sumit Garg <sumit.garg@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Rahul Pathak <rahul@summations.net>,
Anup Patel <anup@brainfault.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
op-tee@lists.trustedfirmware.org,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH RFC 1/5] optee: riscv: add RPMI TEE service group transport
Date: Tue, 15 Sep 2026 22:30:17 -0700 [thread overview]
Message-ID: <a9d9aac7-cb2d-46fe-a220-40f61f615b89@oss.qualcomm.com> (raw)
In-Reply-To: <20260912-rpmi-tee-service-grp-dev-v1-1-1d1d35c2a859@oss.qualcomm.com>
On 9/12/2026 3:15 AM, Amirreza Zarrabi wrote:
> Add an OP-TEE transport for RISC-V using the RPMI TEE service group over
> the SBI MPXY mailbox framework.
>
> Request one mailbox channel per hart and use the channel corresponding to
> the current CPU when issuing a TEE request. Probe the RPMI TEE service
> group and required memory-sharing capabilities before registering the
> transport.
>
> This provides the basic transport and discovery support needed by the
> following patches.
>
> Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
> ---
> drivers/tee/optee/Makefile | 1 +
> drivers/tee/optee/core.c | 8 +-
> drivers/tee/optee/optee_private.h | 34 ++++
> drivers/tee/optee/optee_riscv.c | 312 +++++++++++++++++++++++++++++
> drivers/tee/optee/optee_riscv.h | 141 +++++++++++++
> include/linux/mailbox/riscv-rpmi-message.h | 1 +
> 6 files changed, 495 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/tee/optee/Makefile b/drivers/tee/optee/Makefile
> index ad7049c1c107..925b8ec7ef68 100644
> --- a/drivers/tee/optee/Makefile
> +++ b/drivers/tee/optee/Makefile
> @@ -9,6 +9,7 @@ optee-objs += supp.o
> optee-objs += device.o
> optee-objs += smc_abi.o
> optee-objs += ffa_abi.o
> +optee-$(CONFIG_RISCV_SBI_MPXY_MBOX) += optee_riscv.o
>
> # for tracing framework to find optee_trace.h
> CFLAGS_smc_abi.o := -I$(src)
> diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
> index a52c1f498b99..63f1725e646e 100644
> --- a/drivers/tee/optee/core.c
> +++ b/drivers/tee/optee/core.c
> @@ -220,6 +220,7 @@ void optee_remove_common(struct optee *optee)
>
> static int smc_abi_rc;
> static int ffa_abi_rc;
> +static int riscv_abi_rc;
> static bool intf_is_regged;
>
> static int __init optee_core_init(void)
> @@ -245,9 +246,10 @@ static int __init optee_core_init(void)
>
> smc_abi_rc = optee_smc_abi_register();
> ffa_abi_rc = optee_ffa_abi_register();
> + riscv_abi_rc = optee_riscv_abi_register();
Isn't it growing rapidly now? We have two register calls for the ARM,
one for the RISC-V. One more region specific ISA I am aware of and it
may have op-tee support in future? It is time we fix this logic
in the better way.
>
> - /* If both failed there's no point with this module */
> - if (smc_abi_rc && ffa_abi_rc) {
> + /* If all failed there's no point with this module */
> + if (smc_abi_rc && ffa_abi_rc && riscv_abi_rc) {
This is started looking ugly in my opinion.
> if (IS_REACHABLE(CONFIG_RPMB)) {
> rpmb_interface_unregister(&rpmb_class_intf);
> intf_is_regged = false;
> @@ -270,6 +272,8 @@ static void __exit optee_core_exit(void)
> optee_smc_abi_unregister();
> if (!ffa_abi_rc)
> optee_ffa_abi_unregister();
> + if (!riscv_abi_rc)
> + optee_riscv_abi_unregister();
> }
> module_exit(optee_core_exit);
>
> diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h
> index aefe1e6f5689..8d22d65e087b 100644
> --- a/drivers/tee/optee/optee_private.h
> +++ b/drivers/tee/optee/optee_private.h
> @@ -171,6 +171,31 @@ struct optee_ffa {
> struct work_struct notif_work;
> };
>
> +/**
> + * struct optee_riscv - RPMI TEE communication struct
do we need to name it optee_riscv? we don't use optee_arm anywhere in this
code I believe.
More later...
next prev parent reply other threads:[~2026-09-16 5:30 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-12 10:15 [PATCH RFC 0/5] tee: optee: add RISC-V RPMI TEE transport Amirreza Zarrabi
2026-09-12 10:15 ` [PATCH RFC 1/5] optee: riscv: add RPMI TEE service group transport Amirreza Zarrabi
2026-09-16 5:30 ` Trilok Soni [this message]
2026-09-16 21:23 ` Amirreza Zarrabi
2026-09-17 20:38 ` Trilok Soni
2026-09-12 10:15 ` [PATCH RFC 2/5] optee: riscv: add shared memory and scheduled calls Amirreza Zarrabi
2026-09-12 10:15 ` [PATCH RFC 3/5] optee: riscv: enable persistent shared argument cache Amirreza Zarrabi
2026-09-12 10:15 ` [PATCH RFC 4/5] optee: riscv: add asynchronous notifications over the signal bus Amirreza Zarrabi
2026-09-12 10:15 ` [PATCH RFC 5/5] dt-bindings: tee: add RISC-V RPMI TEE transport Amirreza Zarrabi
2026-09-15 17:13 ` Conor Dooley
2026-09-16 10:12 ` Anup Patel
2026-09-16 21:16 ` Amirreza Zarrabi
2026-09-17 8:38 ` Anup Patel
2026-09-17 19:19 ` Amirreza Zarrabi
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