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Mon, 04 Aug 2025 05:26:38 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5745Qbr3020903 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 4 Aug 2025 05:26:37 GMT Received: from [10.218.33.29] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 3 Aug 2025 22:26:33 -0700 Message-ID: Date: Mon, 4 Aug 2025 10:56:27 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: qcs615: Add OSM l3 interconnect provider node and CPU OPP tables to scale DDR/L3 To: Raviteja Laggyshetty , "Georgi Djakov" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bjorn Andersson" , Konrad Dybcio , Sibi Sankar , Odelu Kukatla , Mike Tipton CC: , , , References: <20250804050542.100806-1-raviteja.laggyshetty@oss.qualcomm.com> <20250804050542.100806-3-raviteja.laggyshetty@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: <20250804050542.100806-3-raviteja.laggyshetty@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: v4oskueLB_Nw6eZ2GoKMkGx_9jOvzuXa X-Authority-Analysis: v=2.4 cv=Y6D4sgeN c=1 sm=1 tr=0 ts=6890448e cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=m_ZRiPf0wcHI9QKGqZsA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: v4oskueLB_Nw6eZ2GoKMkGx_9jOvzuXa X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA0MDAyNSBTYWx0ZWRfX7PezlHO1SWJw Zx1a8IQ+x7HOni44pKU1aCxhArWiHloWHYfOjokoPYshoCurJYO+YpnfHbIbiMEhkR02rkhET2f u7fXu7V5chp9MwyDhtzAzDMJh1vFsFqAERNlqJRG8+yUM4c7k9cc4d/iPPjnYP/clTI3yrrZNRe RPDpPvpHJS3FfNZfc/CsyHUW3ewUFJEZGzP1paVb+gSBVjK5Jl3CKp5QT1p9eR/6v1FqKenoIf8 AXImSy281MEkZ3T2su8JoAtZm5X1t7Om4Mz/1V1tTrzBcpC/NJLhd3LbY6WNz5ICkTRqXi6olKc N0nAmx9UCMFOKiUPLlHnYtdXRK5IVlVkmkjeCNC8DpXhPK4xh2Vbo6l/uSzVMP/wrYhDRXIdYFt JmOMh8J+8kvIpxCFBRFLEePqbnP96GBCVTaT5CoOxLhtg55g7bEmog5iERz4Bu5Bl31JZUvl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-04_02,2025-08-01_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=731 suspectscore=0 clxscore=1011 lowpriorityscore=0 phishscore=0 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508040025 On 8/4/2025 10:35 AM, Raviteja Laggyshetty wrote: > Add Operation State Manager (OSM) L3 interconnect provide node and OPP > tables required to scale DDR and L3 per freq-domain on QCS615 SoC. > As QCS615 and SM8150 SoCs have same OSM hardware, added SM8150 > compatible as fallback for QCS615 OSM device node. > > Signed-off-by: Raviteja Laggyshetty > Signed-off-by: Imran Shaik > --- > arch/arm64/boot/dts/qcom/sm6150.dtsi | 148 +++++++++++++++++++++++++++ > 1 file changed, 148 insertions(+) > This patch is functionally depends on cpufreq-w node change [1]. [1] https://lore.kernel.org/all/20250702-qcs615-mm-cpu-dt-v4-v5-3-df24896cbb26@quicinc.com/ Raviteja, As discussed, please mark the dependency on this change. Thanks, Imran