Re: [PATCH] MIPS: SMP: Implement parallel CPU bring up for EyeQ

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Sun, Apr 13, 2025 at 09:12:32PM +0200, Gregory CLEMENT wrote:
> Added support for starting CPUs in parallel on EyeQ to speed up boot time.
> 
> On EyeQ5, booting 8 CPUs is now ~90ms faster.
> On EyeQ6, booting 32 CPUs is now ~650ms faster.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Hello,
> 
> This patch allows CPUs to start in parallel. It has been tested on
> EyeQ5 and EyeQ6, which are both MIPS64 and use the I6500 design. These
> systems use CPS to support SMP.
> 
> As noted in the commit log, on EyeQ6, booting 32 CPUs is now ~650ms
> faster.
> 
> Currently, this support is only for EyeQ SoC. However, it should also
> work for other CPUs using CPS. I am less sure about MT ASE support,
> but this patch can be a good starting point. If anyone wants to add
> support for other systems, I can share some ideas, especially for the
> MIPS_GENERIC setup that needs to handle both types of SMP setups.
> 
> Gregory
> ---
>  arch/mips/Kconfig                |  2 ++
>  arch/mips/include/asm/topology.h |  3 +++
>  arch/mips/kernel/smp-cps.c       |  2 ++
>  arch/mips/kernel/smp.c           | 18 ++++++++++++++++++
>  4 files changed, 25 insertions(+)

applied to mips-next.

Thomas.

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