From: "Luck, Tony" <tony.luck@intel.com>
To: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: Feng Xu <feng.f.xu@intel.com>, Borislav Petkov <bp@alien8.de>,
James Morse <james.morse@arm.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Robert Richter <rric@kernel.org>, Yi Lai <yi1.lai@intel.com>,
Shawn Fan <shawn.fan@intel.com>,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 6/7] EDAC/{skx_common,i10nm}: Refactor show_retry_rd_err_log()
Date: Thu, 17 Apr 2025 10:44:55 -0700 [thread overview]
Message-ID: <aAE-F4nGjuKX-m3e@agluck-desk3> (raw)
In-Reply-To: <20250417150724.1170168-7-qiuxu.zhuo@intel.com>
On Thu, Apr 17, 2025 at 11:07:23PM +0800, Qiuxu Zhuo wrote:
> + /* CORRERRCNT register parts. */
> + int cecnt_num;
> + u32 cecnt_offsets[NUM_CECNT_REG];
> + u8 cecnt_widths[NUM_CECNT_REG];
YOu have added this "cecnt_widths" field and code to print in different
formats fo value == 4 ("%.8llx") and not 4 ("%.16llx"). But no CPU
(including Granite Rapids added by next patch) has any values other
than "4".
Is there a mistake in the struct reg_rrl defintions where you intended
to have some "8" values somewhere?
Or is this just for symmetry with the ".widths" you have for the
RRL register (which do have varying widths).
-Tony
next prev parent reply other threads:[~2025-04-17 17:44 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-17 15:07 [PATCH 0/7] EDAC/i10nm: Add RRL support for Intel Granite Rapids server Qiuxu Zhuo
2025-04-17 15:07 ` [PATCH 1/7] EDAC/skx_common: Fix general protection fault Qiuxu Zhuo
2025-04-17 15:07 ` [PATCH 2/7] EDAC/{skx_common,i10nm}: Fix the loss of saved RRL for HBM pseudo channel 0 Qiuxu Zhuo
2025-04-17 15:07 ` [PATCH 3/7] EDAC/i10nm: Explicitly set the modes of the RRL register sets Qiuxu Zhuo
2025-04-17 15:07 ` [PATCH 4/7] EDAC/{skx_common,i10nm}: Structure the per-channel RRL registers Qiuxu Zhuo
2025-04-17 15:07 ` [PATCH 5/7] EDAC/{skx_common,i10nm}: Refactor enable_retry_rd_err_log() Qiuxu Zhuo
2025-04-17 15:07 ` [PATCH 6/7] EDAC/{skx_common,i10nm}: Refactor show_retry_rd_err_log() Qiuxu Zhuo
2025-04-17 17:44 ` Luck, Tony [this message]
2025-04-18 2:13 ` Zhuo, Qiuxu
2025-04-18 15:25 ` Luck, Tony
2025-04-19 2:32 ` Zhuo, Qiuxu
2025-04-17 15:07 ` [PATCH 7/7] EDAC/{skx_common,i10nm}: Add RRL support for Intel Granite Rapids server Qiuxu Zhuo
2025-04-18 17:24 ` [PATCH 0/7] EDAC/i10nm: " Luck, Tony
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