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> ranges = <0 0 0 0x80000000>; > > + rtc0: rtc@40060000 { > + compatible = "nxp,s32g2-rtc"; > + reg = <0x40060000 0x1000>; > + interrupts = ; > + clocks = <&clks 54>, <&clks 55>; > + clock-names = "ipg", "source0"; > + }; > + > pinctrl: pinctrl@4009c240 { > compatible = "nxp,s32g2-siul2-pinctrl"; > /* MSCR0-MSCR101 registers on siul2_0 */ > diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi > index b4226a9143c8..e71b80e048dc 100644 > --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi > @@ -171,6 +171,15 @@ soc@0 { > #size-cells = <1>; > ranges = <0 0 0 0x80000000>; > > + rtc0: rtc@40060000 { > + compatible = "nxp,s32g3-rtc", > + "nxp,s32g2-rtc"; > + reg = <0x40060000 0x1000>; > + interrupts = ; > + clocks = <&clks 54>, <&clks 55>; > + clock-names = "ipg", "source0"; > + }; > + > pinctrl: pinctrl@4009c240 { > compatible = "nxp,s32g2-siul2-pinctrl"; > /* MSCR0-MSCR101 registers on siul2_0 */ > -- > 2.45.2 >