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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23603077e9dsm9466565ad.1.2025.06.06.03.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 03:17:52 -0700 (PDT) Date: Fri, 6 Jun 2025 03:17:50 -0700 From: Qiang Yu To: Johan Hovold Cc: Wenbin Yao , catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, sfr@canb.auug.org.au, linux-phy@lists.infradead.org, krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, Johan Hovold , Abel Vesa Subject: Re: [PATCH v4 5/5] phy: qcom: qmp-pcie: add x1e80100 qref supplies Message-ID: References: <20250604080237.494014-1-quic_wenbyao@quicinc.com> <20250604080237.494014-6-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Authority-Analysis: v=2.4 cv=CY8I5Krl c=1 sm=1 tr=0 ts=6842c052 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=6IFa9wvqVegA:10 a=VwQbUJbxAAAA:8 a=zitRP-D0AAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=Kn45tV52aVggcf7Ks3EA:9 a=CjuIK1q_8ugA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=xwnAI6pc5liRhupp6brZ:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: g9QqLKCZ4K2c2zJZ23oIVFqpMT-qs_TT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA2MDA5MyBTYWx0ZWRfX5ccbmkXolF7j j/DrpaliSTJJbNxuaO5Y7ZgcnkwJLcfg1VJ9I0PJmXaGHwmCsx3zJqtF0hlK38vu12ws3jzevzQ pM+tcSeDQRuZTAHjbdI7qSoSyYfeubOy3OakQtxXmNnyk0EWBnpEd2ZqkyZvChRTCa96aKDDH4M 8rjDtI8/FDSPeiCEkpq0m3Pdo0MKxXjxsStecJE/ZUTILHnBTUuBmcWBU7sCbqbBhUf+IeL8UOT 57x/MOlDcd9zlM1YEA1RKSgEdbaMZoYE0DJt3VpIhKrrJHZ9VBOVBPIafAG+pjlA3fYSIQb+xV5 JdtZvYWMYcbyGvFOuTeN3Mcv+UmN8kPYEfmRtotx/Sfms5rWJzzfEg/H4c+ErMTMv8dQSeh9gv3 1A5fVcQfDQit2u9s4sQfy+lF6ur6QXrwA2aDP6brknK7U5b6sUJrmpVJYZHHMkKczmZXsCWI X-Proofpoint-GUID: g9QqLKCZ4K2c2zJZ23oIVFqpMT-qs_TT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-06_03,2025-06-05_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506060093 On Wed, Jun 04, 2025 at 05:10:19PM +0200, Johan Hovold wrote: > On Wed, Jun 04, 2025 at 04:02:37PM +0800, Wenbin Yao wrote: > > From: Qiang Yu > > > > All PCIe PHYs on the X1E80100 SOC require the vdda-qref, which feeds QREF > > clocks provided by the TCSR device. > > As I just mentioned in the thread where this is still being discussed: > > https://lore.kernel.org/all/aEBfV2M-ZqDF7aRz@hovoldconsulting.com > > you need to provide a lot more detail on why you think modelling these > supplies as PHY supplies (which they are not) is the right thing to do. > TCSR_PCIE_xx_CLKREF_EN is not always in TCSR, they're custom bits to enable pieces of the distribution network. We always classify them as "TCSR" even though they're not always in that module. So even if we put the QREF supplies in tscr device tree node, it still doesn't describe the hardware correctly as the hardware itself does't have a unified structure. Since the TCSR_PCIE_xx_CLKREF_EN is only required by PCIe, why can't we model these supplies consumed by TCSR_PCIE_xx_CLKREF_EN as PHY supplies, treating PCIe PHY and TCSR_PCIE_xx_CLKREF_EN as a whole. > Also please answer the question I've asked three times now on how the > QREF supplies map to PHY supplies on X1E as no one will be able to use > this binding unless this is documented somewhere (and similar for other > SoCs). > PCIe3, VDD_A_QREFS_0P875_0, VDD_A_QREFS_0P875_B, VDD_A_QREFS_1P2_B, PCIe4, VDD_A_QREFS_0P875_B, VDD_A_QREFS_1P2_B PCIe5, VDD_A_QREFS_0P875_2, VDD_A_QREFS_0P875_B, VDD_A_QREFS_1P2_B, PCIe6 VDD_A_QREFS_0P875_A, VDD_A_QREFS_1P2_A > The fact that you so far have not been able to provide an answer > seems to suggest that these supplies need to be managed by the TCSR > clock driver which can handle the mapping. > > > Hence, restore the vdda-qref request for the 6th and the 3th PCIe instance > > by reverting commit 031b46b4729b ("phy: qcom: qmp-pcie: drop bogus x1e80100 > > qref supplies") and commit eb7a22f830f6("phy: qcom: qmp-pcie: drop bogus > > x1e80100 qref supply"). For the 4th PCIe instance (Gen3 x2), add a new > > driver data entry, namely x1e80100_qmp_gen3x2_pciephy_cfg, which is a copy > > of sm8550_qmp_gen3x2_pciephy_cfg but uses sm8550_qmp_phy_vreg_l instead. > > > > Fixes: eb7a22f830f6 ("phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies") > > Fixes: 031b46b4729b ("phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies") > > Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE") > > Cc: Johan Hovold > > Cc: Abel Vesa > > Signed-off-by: Qiang Yu > > Signed-off-by: Wenbin Yao > > NAK, for now, and please don't post any new revisions of this patch > until this has been resolved. OK, I will remove this patch from the series if other patches require updates and submit it separately when it is required. - Qiang Yu > > Johan