Re: [PATCH RFC v7 3/3] riscv: mm: Add uffd write-protect support

[Deepak Gupta <debug@rivosinc.com>]

On Wed, Apr 09, 2025 at 05:53:20PM +0800, Chunyan Zhang wrote:
>The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
>for software, this patch uses bit 60 for uffd-wp tracking
>
>Additionally for tracking the uffd-wp state as a PTE swap bit, we borrow
>bit 4 which is not involved into swap entry computation.
>
>Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
>---
> arch/riscv/Kconfig                    |  1 +
> arch/riscv/include/asm/pgtable-bits.h | 18 ++++++++
> arch/riscv/include/asm/pgtable.h      | 65 +++++++++++++++++++++++++++
> 3 files changed, 84 insertions(+)
>
>diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>index 652e2bbfb702..cafdfbe4412b 100644
>--- a/arch/riscv/Kconfig
>+++ b/arch/riscv/Kconfig
>@@ -145,6 +145,7 @@ config RISCV
> 	select HAVE_ARCH_TRACEHOOK
> 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU
> 	select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD
>+	select HAVE_ARCH_USERFAULTFD_WP if 64BIT && MMU && USERFAULTFD && RISCV_ISA_SVRSW60T59B
> 	select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
> 	select HAVE_ASM_MODVERSIONS
> 	select HAVE_CONTEXT_TRACKING_USER
>diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
>index a6fa871dc19e..a953a582cd75 100644
>--- a/arch/riscv/include/asm/pgtable-bits.h
>+++ b/arch/riscv/include/asm/pgtable-bits.h
>@@ -39,6 +39,24 @@
> #define _PAGE_SWP_SOFT_DIRTY	0
> #endif /* CONFIG_MEM_SOFT_DIRTY */
>
>+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
>+
>+/* ext_svrsw60t59b: Bit(60) for uffd-wp tracking */
>+#define _PAGE_UFFD_WP							\
>+	((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?	\
>+	 (1UL << 60) : 0)
>+/*
>+ * Bit 4 is not involved into swap entry computation, so we
>+ * can borrow it for swap page uffd-wp tracking.
>+ */
>+#define _PAGE_SWP_UFFD_WP						\
>+	((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?	\
>+	 _PAGE_USER : 0)
>+#else
>+#define _PAGE_UFFD_WP		0
>+#define _PAGE_SWP_UFFD_WP	0
>+#endif
>+

Same comment as previous patch on above. Have `RISCV_ISA_EXT_SVRSW60T59B`
with the "#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP"


> #define _PAGE_TABLE     _PAGE_PRESENT
>
> /*
>diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>index 14461ffe6321..ee0fbca28a76 100644
>--- a/arch/riscv/include/asm/pgtable.h
>+++ b/arch/riscv/include/asm/pgtable.h
>@@ -425,6 +425,38 @@ static inline pte_t pte_wrprotect(pte_t pte)
> 	return __pte(pte_val(pte) & ~(_PAGE_WRITE));
> }
>
>+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
>+static inline bool pte_uffd_wp(pte_t pte)
>+{
>+	return !!(pte_val(pte) & _PAGE_UFFD_WP);
>+}
>+
>+static inline pte_t pte_mkuffd_wp(pte_t pte)
>+{
>+	return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD_WP));
>+}
>+
>+static inline pte_t pte_clear_uffd_wp(pte_t pte)
>+{
>+	return __pte(pte_val(pte) & ~(_PAGE_UFFD_WP));
>+}
>+
>+static inline bool pte_swp_uffd_wp(pte_t pte)
>+{
>+	return !!(pte_val(pte) & _PAGE_SWP_UFFD_WP);
>+}
>+
>+static inline pte_t pte_swp_mkuffd_wp(pte_t pte)
>+{
>+	return __pte(pte_val(pte) | _PAGE_SWP_UFFD_WP);
>+}
>+
>+static inline pte_t pte_swp_clear_uffd_wp(pte_t pte)
>+{
>+	return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD_WP));
>+}
>+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
>+
> /* static inline pte_t pte_mkread(pte_t pte) */
>
> static inline pte_t pte_mkwrite_novma(pte_t pte)
>@@ -853,6 +885,38 @@ static inline pud_t pud_mkspecial(pud_t pud)
> }
> #endif
>
>+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
>+static inline bool pmd_uffd_wp(pmd_t pmd)
>+{
>+	return pte_uffd_wp(pmd_pte(pmd));
>+}
>+
>+static inline pmd_t pmd_mkuffd_wp(pmd_t pmd)
>+{
>+	return pte_pmd(pte_mkuffd_wp(pmd_pte(pmd)));
>+}
>+
>+static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd)
>+{
>+	return pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd)));
>+}
>+
>+static inline bool pmd_swp_uffd_wp(pmd_t pmd)
>+{
>+	return pte_swp_uffd_wp(pmd_pte(pmd));
>+}
>+
>+static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd)
>+{
>+	return pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd)));
>+}
>+
>+static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd)
>+{
>+	return pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd)));
>+}
>+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
>+
> #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> static inline bool pmd_soft_dirty(pmd_t pmd)
> {
>@@ -978,6 +1042,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
>  *	bit            0:	_PAGE_PRESENT (zero)
>  *	bit       1 to 2:	(zero)
>  *	bit            3:	_PAGE_SWP_SOFT_DIRTY
>+ *	bit            4:	_PAGE_SWP_UFFD_WP
>  *	bit            5:	_PAGE_PROT_NONE (zero)
>  *	bit            6:	exclusive marker
>  *	bits      7 to 11:	swap type
>-- 
>2.34.1
>