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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?a45xu//s+BbvTLFK+Hpj/JKAGwhjfYDw30UI7Yy1E2yhDcJJT9w1W9iUeJAb?= =?us-ascii?Q?4l4tnO3TgwDtZ9/dE19ASfFoUd+hk3VOSAfCdmG5sSqwR50R7tl/ChJaGjPF?= =?us-ascii?Q?GWwYCy4r4VEg/bdJwllKnLKfvfiRoMhdFJ81EBaFVtlZn16C06nsJGTRTthO?= =?us-ascii?Q?UgrqOBn68wAWZwfALrCkBRMBZ9GZ8W6jGTkDxXN/ogkGET4pFskFCBNXOgpo?= =?us-ascii?Q?gQEL7lSzHHc6MTu8C7yaFJYOT5dBT6DbaputbcF+Bb8DKraZRbnRaNYHiCO9?= =?us-ascii?Q?cZwgRCTfeUsPYfYSFA+eFeloZkxPTJknqcs2zbuLmJ0OQFAeNipVLC6IbcGh?= =?us-ascii?Q?HsHMSTIjRkzIZ770RWH9Nu46q2EgOsebzxLJt2HVkA+RbpfnTPz/ziB0R6SD?= =?us-ascii?Q?oG733+53tQeT+5AC1Hi26mXruQTcE99OvtWJfQ+lrALweUh/pf1ssjhtgYPX?= =?us-ascii?Q?tuRcFoSeWvGb6I6LHs/IBSgcUezyCb0sJKWu9UCl+2IkJKR5UMR4rjkRaNh/?= =?us-ascii?Q?kkTamUe43zNYUHFQaUltN+EA+FXdpjyBFVfcnMYti2d6tyQ0+N8wLidtUswf?= =?us-ascii?Q?I3jjgzET6V+giwk2OI7EUZhZuVw2Z6g3Q5SyCuW4DkVxTZldY7U2UXfmkr/H?= =?us-ascii?Q?yPdrQ8elo9ez73JucH/HtFwBMLROmnDETIMauFKQYL/ZmFJmu2Dzx3e6U8Kd?= =?us-ascii?Q?n1NZAJnCP5lm/NMolw3JsIsefa7GYfpYanhZgHjaeumicAwzAu1ezSeb4qV2?= =?us-ascii?Q?ZK/fPrsKaB+Rxtt4C0uxlQlxxu49CgVA30uMfvWnwSpaiXewbRTUnrkG/qCd?= =?us-ascii?Q?bsThq5V4UlsWzy5erUJ+UAMViYGyUjMfkuBD4Do1+TitZzmLjfgzthE+d7NF?= =?us-ascii?Q?9LNxpOoc9EOX5IoOAAmAHk34b91m0+yCl5eEL0UaqRoBXtMa4XihCQQUkoKf?= =?us-ascii?Q?6RNIXDfL9j9hDL42MsOacnwv4Uye2nHRIORFuiKR8nrsKei6mzfMwuzX5i33?= =?us-ascii?Q?BTjoSakNNMP1h0V73If3cq+BG39SJswBFJyqysY70bHRBzcI3yNpF8JHfrcG?= =?us-ascii?Q?E2Esk9KArgtnEbvK8dpIJrQgqk4PjfITWpLPDbOtgIcq259FC326AbDYXll1?= =?us-ascii?Q?//sBpifZkiJuFTjNxjSOVpNlYI7s6quNRf8m55aI+A/PQLSpe+KUg46O0zIw?= =?us-ascii?Q?HQexqEk75RsbesgV7vMbwjEoS9YON4wU/rq2UmR3HpBsu9oAzbmCkfF5UNvx?= =?us-ascii?Q?I696Fghsq2Kk0WxUcReomNBL//RxMtVJbyYCZfVD1f1MuGGD/0dqlo+MpxqR?= =?us-ascii?Q?HRWxUqZR8Po+ciWkYOge+gyjbP9BCO7G4jG5XuDfDZZcZ5wawJFDk3bxLfnd?= =?us-ascii?Q?k66aq7pOUQOsKwejSgR3iaA70akqfvfyZ//YP7+cB58lP1/o/z0cGaxPgWwD?= =?us-ascii?Q?01sNWS8kuhqc6yaQRrm8LNKMZ9hIoDfFwnxcKi1wLhuA2wo8oAWw4dj2GHY3?= =?us-ascii?Q?rfn6KbmTT2OSIacldnUfgHG11H8BGrCL++uZYLFQvqZb3qCuSOta4/c7ggRb?= =?us-ascii?Q?UEXwKJ+lzRaG0Z59K7s=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 74df5005-4242-4042-5827-08dda917247c X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2025 18:38:22.0012 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2p2RAeNyDidVcrAOhic7jdfo8wXAV/2newg8XBkD/FnFmW5WwsC99QIiDX0wmMsqo/ezrTH4MVOLw+lYDn/LZQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB9057 On Thu, Jun 12, 2025 at 12:31:21AM +0800, Hans Zhang wrote: Subject should be PCI: dwc: imx6: Refactor code by using dw_pcie_clear_and_set_dword() tag "imx6:" should after "dwc:" Reviewed-by: Frank Li > i.MX6 PCIe driver contains multiple read-modify-write sequences for > link training and speed configuration. These operations manually handle > bit masking and shifting to update specific fields in control registers, > particularly for link capabilities and speed change initiation. > > Refactor link capability configuration and speed change handling using > dw_pcie_clear_and_set_dword(). The helper simplifies LNKCAP modification > by encapsulating bit clear/set operations and eliminates intermediate > variables. For speed change control, replace explicit bit manipulation > with direct register updates through the helper. > > Adopting the standard interface reduces code complexity in link training > paths and ensures consistent handling of speed-related bits. The change > also prepares the driver for future enhancements to Gen3 link training > by centralizing bit manipulation logic. > > Signed-off-by: Hans Zhang <18255117159@163.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 26 ++++++++++---------------- > 1 file changed, 10 insertions(+), 16 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 5a38cfaf989b..3004e432f013 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -941,7 +941,6 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > struct imx_pcie *imx_pcie = to_imx_pcie(pci); > struct device *dev = pci->dev; > u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > - u32 tmp; > int ret; > > if (!(imx_pcie->drvdata->flags & > @@ -956,10 +955,9 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > * bus will not be detected at all. This happens with PCIe switches. > */ > dw_pcie_dbi_ro_wr_en(pci); > - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > - tmp &= ~PCI_EXP_LNKCAP_SLS; > - tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); > + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, > + PCI_EXP_LNKCAP_SLS, > + PCI_EXP_LNKCAP_SLS_2_5GB); > dw_pcie_dbi_ro_wr_dis(pci); > > /* Start LTSSM. */ > @@ -972,18 +970,16 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > > /* Allow faster modes after the link is up */ > dw_pcie_dbi_ro_wr_en(pci); > - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > - tmp &= ~PCI_EXP_LNKCAP_SLS; > - tmp |= pci->max_link_speed; > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); > + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, > + PCI_EXP_LNKCAP_SLS, > + pci->max_link_speed); > > /* > * Start Directed Speed Change so the best possible > * speed both link partners support can be negotiated. > */ > - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > - tmp |= PORT_LOGIC_SPEED_CHANGE; > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); > + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, > + 0, PORT_LOGIC_SPEED_CHANGE); > dw_pcie_dbi_ro_wr_dis(pci); > > ret = imx_pcie_wait_for_speed_change(imx_pcie); > @@ -1295,7 +1291,6 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > struct imx_pcie *imx_pcie = to_imx_pcie(pci); > - u32 val; > > if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_8GT_ECN_ERR051586) { > /* > @@ -1310,9 +1305,8 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > * to 0. > */ > dw_pcie_dbi_ro_wr_en(pci); > - val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > - val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); > + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, > + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0); > dw_pcie_dbi_ro_wr_dis(pci); > } > } > -- > 2.25.1 >