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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?fuxPQIIbLwiyaIp/W9Cw8SckBZF6toP7s/w8BQpPLwVzxaxoxXKsUmmrMijw?= =?us-ascii?Q?DiUxb8BVPCtMtXBuE2MOvWK4cFJu+RRdZJzikTA4r7j6T/7NPweFT4q1bfCL?= =?us-ascii?Q?l165jECd6V7RosFIIiMpa+UhjtHKO4is1yqa5yHQLaJ3YRKSI23j4wnS1sGU?= =?us-ascii?Q?U/gK6mgOlxIPAPWwTmj7/vaAN4olI1MoKKDBi1dNJ8Y2ZbEh3MdgFTpvCM0F?= =?us-ascii?Q?vzYb3WTH9MwSfsOAu5AScq/DG3y7NMtEbdvjO84KtuYq7tvNTvMx2OAHfPrp?= =?us-ascii?Q?NIgruad8sUrFDTy2r22nm6/UFbjCs5+uJes0NX+6IFt1xVrBFtxbGKrOqNpC?= =?us-ascii?Q?OqG7lzLMb+VRDtQcSE5jIzC63zKQWDKLa6NrlQ/whweH4bB72bvzWTz+YcKW?= =?us-ascii?Q?u2242kgkaAVijq/5i6Vll0B4YufAu6YIqo1v+N8s8oO5y9ICsaqlr+58ECE8?= =?us-ascii?Q?5v+2auTC85Yt1pJnOILxm9nfPWlPrW4/at2G7QbHQ5AkjdUsrSQDt2DTfQZD?= =?us-ascii?Q?jZxQJJjvTpz1QTHcJZqzu4/sDO62q8lwG9OxotCG/rClYp0em/tMWjkOGXmM?= =?us-ascii?Q?hhccf9Yu05CdwJGNFJjeHfA7EC4F+3nqjnNs9R12KhZIt4j3dwCdoRJV1hOL?= =?us-ascii?Q?moIHHerUw9id+N2VyZ6cgpm0gWhUB1EYAwWDYDe/fUZAi+193+4Orws7iBEh?= =?us-ascii?Q?4MgBmRtlqEqG0doRDFXjr89jeDb0aMI8rSwaEflKElcLcdxEr4RYHc7kz6rT?= =?us-ascii?Q?/ruyPjcOeMWuDD83hdWqF+H+ZMaGinGsQQqGR0B57LB3bvvqmO/mnlzDlkFv?= =?us-ascii?Q?JDEYkwrzkKccPBgyMg1ayXiyVuAxCUpckfQbvD/Ch2H7T9IEJIGtHPzQJPcK?= =?us-ascii?Q?zpbDh2cUMZJa8+vVfhmsJnMcfInwDOKuzXuB7k/6R5qepEfBGVGs7tgciG2t?= =?us-ascii?Q?q+ABjTcy4LFug6pHN7L+c0mSaOBmXZ4HUl/NjmT96Kc65rOKWLt2P7w/DCVI?= =?us-ascii?Q?MtBwH76MDlhxmicvv3d3t/npK3Q9sRJtOoUhU1FXUfRAFRvelifXKVH8S3MS?= =?us-ascii?Q?QEuhToyg5KJ6EayJ6C90QnQO2ZKuTjvrlIYtuYo8/OvWzTxKAx84dF8cEGgg?= =?us-ascii?Q?RU6ZDL2m6Qb+fYZtMAt0PDuyTuQrMXjSBdi3sapmG/rwAgCh9nam54MvSQTi?= =?us-ascii?Q?R6LlNnCVyJpmf9/4tkadQbKoj/YIcLGiCR1iUv76RwgrT6PvyzyXu57VFjVY?= =?us-ascii?Q?2mYns9XI+MpSpcVpaYPY/ry9Bf7CMohDT/PHycLmuSLpnQgXg/rLZqVBnj1f?= =?us-ascii?Q?jBNw75KWaHhqUtW78LeXabvDz6iPYxbOYzrY4uVlbV8f4NaKR+D0nsUx+3hl?= =?us-ascii?Q?kgALbVIYG7H+5FZ9fP07zGke5BUbpYoXY7DI2zsHDBErP/355W23d4n5ZzBV?= =?us-ascii?Q?36KNIXHilSKbD9jhCcsSjlS0iKZ9lp5Hvz/g/627EWBXDONPaB9p1g7n7b+6?= =?us-ascii?Q?Le3HVeHCgiH8yeZRL2967WvyPBB4b6oS1+j88HSpyZMYIbifmON+mPNkgW9P?= =?us-ascii?Q?gbtM8NI7Zab2e3WtDRFoyLrZyRashFusQpr7qwMd?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0f5257f4-e14e-4c05-cee1-08dda91835c9 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2025 18:46:00.4842 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: UU2mqgPrQMCPpJjfGFxhwKhUyrA42wJCcYmKvZZ827KUR46wxqF4G1UUgH95nU1qIRm0d21zZeUqhPstb328fQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR04MB7362 On Wed, Jun 11, 2025 at 02:38:14PM -0400, Frank Li wrote: > On Thu, Jun 12, 2025 at 12:31:21AM +0800, Hans Zhang wrote: > > Subject should be > > PCI: dwc: imx6: Refactor code by using dw_pcie_clear_and_set_dword() > > tag "imx6:" should after "dwc:" > > Reviewed-by: Frank Li I sent out too quick, please don't applied my review tag at next version because I found a issue, see: https://lore.kernel.org/linux-pci/aEnONwJUSEMdMAUD@lizhi-Precision-Tower-5810/ Frank > > > i.MX6 PCIe driver contains multiple read-modify-write sequences for > > link training and speed configuration. These operations manually handle > > bit masking and shifting to update specific fields in control registers, > > particularly for link capabilities and speed change initiation. > > > > Refactor link capability configuration and speed change handling using > > dw_pcie_clear_and_set_dword(). The helper simplifies LNKCAP modification > > by encapsulating bit clear/set operations and eliminates intermediate > > variables. For speed change control, replace explicit bit manipulation > > with direct register updates through the helper. > > > > Adopting the standard interface reduces code complexity in link training > > paths and ensures consistent handling of speed-related bits. The change > > also prepares the driver for future enhancements to Gen3 link training > > by centralizing bit manipulation logic. > > > > Signed-off-by: Hans Zhang <18255117159@163.com> > > --- > > drivers/pci/controller/dwc/pci-imx6.c | 26 ++++++++++---------------- > > 1 file changed, 10 insertions(+), 16 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > > index 5a38cfaf989b..3004e432f013 100644 > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > @@ -941,7 +941,6 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > > struct imx_pcie *imx_pcie = to_imx_pcie(pci); > > struct device *dev = pci->dev; > > u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > > - u32 tmp; > > int ret; > > > > if (!(imx_pcie->drvdata->flags & > > @@ -956,10 +955,9 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > > * bus will not be detected at all. This happens with PCIe switches. > > */ > > dw_pcie_dbi_ro_wr_en(pci); > > - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > > - tmp &= ~PCI_EXP_LNKCAP_SLS; > > - tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; > > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); > > + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, > > + PCI_EXP_LNKCAP_SLS, > > + PCI_EXP_LNKCAP_SLS_2_5GB); > > dw_pcie_dbi_ro_wr_dis(pci); > > > > /* Start LTSSM. */ > > @@ -972,18 +970,16 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > > > > /* Allow faster modes after the link is up */ > > dw_pcie_dbi_ro_wr_en(pci); > > - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > > - tmp &= ~PCI_EXP_LNKCAP_SLS; > > - tmp |= pci->max_link_speed; > > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); > > + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, > > + PCI_EXP_LNKCAP_SLS, > > + pci->max_link_speed); > > > > /* > > * Start Directed Speed Change so the best possible > > * speed both link partners support can be negotiated. > > */ > > - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > > - tmp |= PORT_LOGIC_SPEED_CHANGE; > > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); > > + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, > > + 0, PORT_LOGIC_SPEED_CHANGE); > > dw_pcie_dbi_ro_wr_dis(pci); > > > > ret = imx_pcie_wait_for_speed_change(imx_pcie); > > @@ -1295,7 +1291,6 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > > { > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > struct imx_pcie *imx_pcie = to_imx_pcie(pci); > > - u32 val; > > > > if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_8GT_ECN_ERR051586) { > > /* > > @@ -1310,9 +1305,8 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > > * to 0. > > */ > > dw_pcie_dbi_ro_wr_en(pci); > > - val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > > - val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > > - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); > > + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, > > + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0); > > dw_pcie_dbi_ro_wr_dis(pci); > > } > > } > > -- > > 2.25.1 > >