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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?igp5sflXOqma5onU3JaK8x5GLIEiwWEZ3xPdzfJlAoenNH26X8HtiKBP+BIs?= =?us-ascii?Q?6F/hZ/TksBfT7bBHJHMSVxpRyx8h5QATwTDMtMNK0z5oB/Y2JZQCUxUyOlLW?= =?us-ascii?Q?v3yxxLCEe5cpu/a0YdsTYjJO0z1ecm798vmOHpnq55xe+tukL2lr00hOo+0i?= =?us-ascii?Q?h8hgNUJceaYG9M/8azvzjYJl7yvgHEmz6MTSRbmCA0K5BDFpsF36RUMcIG8S?= =?us-ascii?Q?A0DenPflev6klcz62Y6fBwetkK2XgfAS5/uz415gPwkhVhotSA1dTTLII7DY?= =?us-ascii?Q?JI2deGmXMM3CbqTi5wTp3/mmKWU+49fqkU1o/L9F52eos4hQzGogSAt1hz0i?= =?us-ascii?Q?eOp3LEW356eNv8z7DlH3/xWYWfhAyy+5oMJ/RoogS9IBT6Q+DCBorkaXXwdp?= =?us-ascii?Q?Nhyfy9gWuKzLM8/WrozwMH1pbQ8dABGoF2UgRu2XdpbsNbnAQCQPXLvJ7Tt1?= =?us-ascii?Q?swg1JilraGzf17uKvNG7KCZzCSUDHFmB5gNbFcHjzSE4PbbzvWCzcwnUV0/r?= =?us-ascii?Q?AsegtaXxj3CqPE1h/l8OhhB3R4wLswl7J9z4nZOUJIisq4/DBiVH+ZrW7znB?= =?us-ascii?Q?DT765ko2Blrxb+xV0vgSPYzHQ+Whn+T8SuKbATiNnpi6qFOxECoMPgqYfO//?= =?us-ascii?Q?7V+B2wQzCdsqCGD58fvc5BdFyTCHpj+7icNf66Hs5sDPstYaTgQ4mn3358+l?= =?us-ascii?Q?jQ0rdONzh5p4/+wKzyHaDMIVl6grO+0xBG9yL38KKbq0YXuWzXN5Tkewe12z?= =?us-ascii?Q?R1+E0XsNF0ZmXLAzS6T32Rg+OevL2IYWEcJfPW9zFZhdnrqEvtCqBSozqUKf?= =?us-ascii?Q?GwdC8IqfmL34WTwQGDT6dWTpr51MUcTnfSfG1plk7fFtI0gFAfaaRwSKak59?= =?us-ascii?Q?wKhwJf7/JDPOGKIpR1/zUhOstNDNlq+AhBIMtRFPIplbIfEPK5F11prH/Glx?= =?us-ascii?Q?57G6zRjDxf5rKTuDNLKDJASVeQwDs1J1uen8/1lklAaVXAlkSGwLBCUJHfCz?= =?us-ascii?Q?U8X9xf2BMN6BDaGDTtQo/vQCwwXLRoyfISya1WAwBrbWSwXwqYBzsKS7KEc8?= =?us-ascii?Q?gm9OzgxbulChAYGMicTYLISkDIZfO0OTt3vU6/L87xNKyIVzJzMC3MsGCz8y?= =?us-ascii?Q?y4BlLt3QHggA8Ph4UH1QeJAPRs5I/UsB367UcscgiYRafJnj70U4f67X5hcP?= =?us-ascii?Q?UZDSlUy36bey+7a8mJecDqwKr5Cd82cyucs3P7F/7HAu1iOYInjVtJtfhJmC?= =?us-ascii?Q?FakG0knJddDefxyK4tPi/Uejs5j3P8HYb+9edYIz5ESEJzE4taeGgllap22P?= =?us-ascii?Q?ZvfvhDSlqlx/bLVihDzyIhKWcqMG3ve/aLwy1VmYOTcqkjV2duvcc0SOkOWZ?= =?us-ascii?Q?oeDp+Hmbg8YZFbJ/rYgl0FyJgcp+FDcMwsnvVl3a1JwY/kMtlDZ2heOugCxV?= =?us-ascii?Q?FWaJBiVl2/4iUp9IhqEsqxFcinScsxFuF50hw8zqdVyvShRahD5NgnYgor+y?= =?us-ascii?Q?XM378oCuFNUmM8jDXszwv1sG59T+hukZi/95WHIZN48J+T6N5bgEv0sB1bKh?= =?us-ascii?Q?vig86jvikQfunQ8RrU0hF9qsgt1nqsl3+RAb0J/X?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e1451076-b5ab-4cf4-21b5-08dda917d076 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2025 18:43:10.4569 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WzPgqafyWPZJjn1iIyiFti0FABqHGqK3DawoNg8E3ByU+E7dFLVLxIh88NX0lVNFdpmsM367C3OCKzO/BKBfvQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR04MB7362 On Thu, Jun 12, 2025 at 12:31:21AM +0800, Hans Zhang wrote: > i.MX6 PCIe driver contains multiple read-modify-write sequences for > link training and speed configuration. These operations manually handle > bit masking and shifting to update specific fields in control registers, > particularly for link capabilities and speed change initiation. > > Refactor link capability configuration and speed change handling using > dw_pcie_clear_and_set_dword(). The helper simplifies LNKCAP modification > by encapsulating bit clear/set operations and eliminates intermediate > variables. For speed change control, replace explicit bit manipulation > with direct register updates through the helper. > > Adopting the standard interface reduces code complexity in link training > paths and ensures consistent handling of speed-related bits. The change > also prepares the driver for future enhancements to Gen3 link training > by centralizing bit manipulation logic. > Sorry, where define dw_pcie_clear_and_set_dword() ? > Signed-off-by: Hans Zhang <18255117159@163.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 26 ++++++++++---------------- > 1 file changed, 10 insertions(+), 16 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 5a38cfaf989b..3004e432f013 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -941,7 +941,6 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > struct imx_pcie *imx_pcie = to_imx_pcie(pci); > struct device *dev = pci->dev; > u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > - u32 tmp; > int ret; > > if (!(imx_pcie->drvdata->flags & > @@ -956,10 +955,9 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > * bus will not be detected at all. This happens with PCIe switches. > */ > dw_pcie_dbi_ro_wr_en(pci); > - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > - tmp &= ~PCI_EXP_LNKCAP_SLS; > - tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); > + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, > + PCI_EXP_LNKCAP_SLS, > + PCI_EXP_LNKCAP_SLS_2_5GB); > dw_pcie_dbi_ro_wr_dis(pci); > > /* Start LTSSM. */ > @@ -972,18 +970,16 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > > /* Allow faster modes after the link is up */ > dw_pcie_dbi_ro_wr_en(pci); > - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > - tmp &= ~PCI_EXP_LNKCAP_SLS; > - tmp |= pci->max_link_speed; > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); > + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, > + PCI_EXP_LNKCAP_SLS, > + pci->max_link_speed); > > /* > * Start Directed Speed Change so the best possible > * speed both link partners support can be negotiated. > */ > - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > - tmp |= PORT_LOGIC_SPEED_CHANGE; > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); > + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, > + 0, PORT_LOGIC_SPEED_CHANGE); supposed 3 args is mask. 0 should be PORT_LOGIC_SPEED_CHANGE. Frank > dw_pcie_dbi_ro_wr_dis(pci); > > ret = imx_pcie_wait_for_speed_change(imx_pcie); > @@ -1295,7 +1291,6 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > struct imx_pcie *imx_pcie = to_imx_pcie(pci); > - u32 val; > > if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_8GT_ECN_ERR051586) { > /* > @@ -1310,9 +1305,8 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > * to 0. > */ > dw_pcie_dbi_ro_wr_en(pci); > - val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > - val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); > + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, > + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0); > dw_pcie_dbi_ro_wr_dis(pci); > } > } > -- > 2.25.1 >