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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?VJOsVzxukWpBoFzwYfIrCpPeYg0AqOfG2oxkg0UOmHBiULqovKyyAJhvpxao?= =?us-ascii?Q?r1zOOpaWABLzNLiUfEYkZMAeGVhFqTJP+qJP4hyWUSbvNbDFJYs+EhzM+p7V?= =?us-ascii?Q?dCWYdHSM/FFqsCGFIRQLgBHokE8xxMvhTLWAd+cMVXyIIsrpE2zAQ/SYqTPM?= =?us-ascii?Q?5ZgD9Feodh7mKajVy4xmnDsTFpsUML+9maekdZCRDE4aItShKPIATvRrSgbp?= =?us-ascii?Q?CYFQX5wbEFAyAQbgCwXlkUf7mVswv6A91EfvBirasrj8mxC1ngrDYmyzjTjJ?= =?us-ascii?Q?l2+0f1m20RmFInfsk2LDKhf8BxdITn1Cw++ZiimKE3qZm/oRfv9yDlD7rYJV?= =?us-ascii?Q?mWJoiydDfMeKXtE+47HXkihESlsINl6djtVDJPIhPqsdJ4+dP7tqjp2i/b55?= =?us-ascii?Q?nXjxvAKNRLaKZMnYVHRYW2ch0FQ8MQ6DmOihnvtMzl/vdI9L/sP9WkIQ1WZ8?= =?us-ascii?Q?pHCGIDai3p8xAxXVsVoptH13F6KpfopwCu1IpSZYvGdhwNjJYYqdGR8pYiVn?= =?us-ascii?Q?Hye3rJWNkf8Epo6eLuXTBPNzuP8kICUb7WlGKmx7UPzFy6nHWttmlxacJREa?= =?us-ascii?Q?qLpuxGqHxrJz0bhC80D5OILAwPm9UQ3r8+P9BWCyBi8oF0zSEDZlTyF86+ak?= =?us-ascii?Q?8QpUyp1f4ftD/iwrzNOQVtUbfw7ZPD5ulWTb8pkengM4K9xobOfdXvDMhQNz?= =?us-ascii?Q?L88FvnFo7JxrB+OfjiNM0026l1xtiYMMBKZFgjXTifuSdOrWfnXkUgA4RtMo?= =?us-ascii?Q?JdhQ7WGFOs3k1cl70Js1JwSBpEmFRHqMq+B/IWWJhwvCQStSEXYPjFOmuZdk?= =?us-ascii?Q?Lu9yT/iNJFnGFMO6d6nFGWxrxgzEwjGDsjusPmvAnlJWskq2MlRBDMYJ9DvP?= =?us-ascii?Q?17lwHDwS7icJuNYJba8HT3huVbl/LkfA4RmRiL84hl8nWlHW3pydO3+a+U+9?= =?us-ascii?Q?pOboeSonyPS+m9tb7jRYkrTf6RZCm03VjeodA7ZUh9cJKH1uj95jazTqKMMU?= =?us-ascii?Q?qmnuZmX0Rg/+e0IQ+/xkaz2SsA1js4qpN6bQ4nyhZeAI6elBPk1tuxB+znB5?= =?us-ascii?Q?ps5Ujx9Uy7GiaeMHF2aJfw31aa+eVeCGinPJ9m4+Y90Mnjag45ndGaKBghU5?= =?us-ascii?Q?F1ZezQY2xWFeIgsaTPP6pWPtq8z3RUIUHF2QaQe8LgX2Dx1hqo1rw333UF1x?= =?us-ascii?Q?fE6h4dihreP4A4qlk/pqbapPQ2LgLl4cdWCcHq2zh0jc4jfSjqEDYj6RF10N?= =?us-ascii?Q?s4GrpEEwWcLr/Ca+RASp9xx1j+TDAzwHUxVhjXUSzHbJ2SN51OF6LHp+6+IG?= =?us-ascii?Q?hxd6tqXK5IBeSZ+5w1YWu33agbDa1uTfHA7BuscbA69NBZ9WetfXWWTkEWXT?= =?us-ascii?Q?pEUmQg4c+EPhmidwTBOqc4GFBPaYPRUyOE/t729CYw3aA2hWfPgJwQN1S64L?= =?us-ascii?Q?QB3DMJrUPpBmC+n1CSZEogGFXP5N+i+GDb9O//qnrv5Mgizo6qb0n1sc7C35?= =?us-ascii?Q?T3mgdgxK+NqQMyK8z+tHf0C381At6N85hLdZ9OaLUNi8FglQf8QHgvhmEYKE?= =?us-ascii?Q?J6tIplI/RsV6URasUpAy4lQK2JSixPXRo9rklZ1S?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1648e079-a87d-4dcc-297c-08ddb4d462d5 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 17:10:44.2672 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: C0l9kDtr4lYzy7BJXV/Cz5efEzG88Sz1AbN33SVhzf9eJ11t1htwbG7faOMNmW9ovvkBsNhUF4egxEC8JrAWpw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB9397 On Thu, Jun 26, 2025 at 10:50:31PM +0800, Hans Zhang wrote: > i.MX6 PCIe driver contains multiple read-modify-write sequences for > link training and speed configuration. These operations manually handle > bit masking and shifting to update specific fields in control registers, > particularly for link capabilities and speed change initiation. > > Refactor link capability configuration and speed change handling using > dw_pcie_clear_and_set_dword(). The helper simplifies LNKCAP modification > by encapsulating bit clear/set operations and eliminates intermediate > variables. For speed change control, replace explicit bit manipulation > with direct register updates through the helper. > > Adopting the standard interface reduces code complexity in link training > paths and ensures consistent handling of speed-related bits. The change > also prepares the driver for future enhancements to Gen3 link training > by centralizing bit manipulation logic. > > Signed-off-by: Hans Zhang <18255117159@163.com> missed my review tag, you need collect all review tags when respin patches. Reviewed-by: Frank Li https://lore.kernel.org/linux-pci/aFQp4MYpRaEUXNQy@lizhi-Precision-Tower-5810/ > --- > drivers/pci/controller/dwc/pci-imx6.c | 26 ++++++++++---------------- > 1 file changed, 10 insertions(+), 16 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 5a38cfaf989b..3004e432f013 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -941,7 +941,6 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > struct imx_pcie *imx_pcie = to_imx_pcie(pci); > struct device *dev = pci->dev; > u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > - u32 tmp; > int ret; > > if (!(imx_pcie->drvdata->flags & > @@ -956,10 +955,9 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > * bus will not be detected at all. This happens with PCIe switches. > */ > dw_pcie_dbi_ro_wr_en(pci); > - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > - tmp &= ~PCI_EXP_LNKCAP_SLS; > - tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); > + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, > + PCI_EXP_LNKCAP_SLS, > + PCI_EXP_LNKCAP_SLS_2_5GB); > dw_pcie_dbi_ro_wr_dis(pci); > > /* Start LTSSM. */ > @@ -972,18 +970,16 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > > /* Allow faster modes after the link is up */ > dw_pcie_dbi_ro_wr_en(pci); > - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > - tmp &= ~PCI_EXP_LNKCAP_SLS; > - tmp |= pci->max_link_speed; > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); > + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, > + PCI_EXP_LNKCAP_SLS, > + pci->max_link_speed); > > /* > * Start Directed Speed Change so the best possible > * speed both link partners support can be negotiated. > */ > - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > - tmp |= PORT_LOGIC_SPEED_CHANGE; > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); > + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, > + 0, PORT_LOGIC_SPEED_CHANGE); > dw_pcie_dbi_ro_wr_dis(pci); > > ret = imx_pcie_wait_for_speed_change(imx_pcie); > @@ -1295,7 +1291,6 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > struct imx_pcie *imx_pcie = to_imx_pcie(pci); > - u32 val; > > if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_8GT_ECN_ERR051586) { > /* > @@ -1310,9 +1305,8 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > * to 0. > */ > dw_pcie_dbi_ro_wr_en(pci); > - val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > - val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); > + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, > + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0); > dw_pcie_dbi_ro_wr_dis(pci); > } > } > -- > 2.25.1 >