Re: [PATCH 1/1] PCI: Fix secondary bus wait return value when D3cold delay = 0

[Lukas Wunner <lukas@wunner.de>]

On Tue, Jun 10, 2025 at 02:55:31PM +0300, Ilpo Järvinen wrote:
> If D3cold delay is zero, pci_bridge_wait_for_secondary_bus()
> immediately returns 0 which is inconsistent with the rest of the
> function.
> 
> When D3cold delay is 0, infer the return value like in the other cases.
> With link_active_reporting, use Data Link Layer Link Active (PCIe spec
> r6.2 sec. 7.5.3.8) and otherwise call pci_dev_wait() with zero delay.

I guess Mika implemented it this way on purpose:

If d3cold_delay is zero, the devices on the secondary bus are
immediately available and there's no need to wait.  Note that
pci_bus_max_d3cold_delay() goes below the default min_delay of 100
only if pdev->d3cold_delay is lower.

And pci_pm_init() initializes d3cold_delay to PCI_PM_D3COLD_WAIT
(which is also 100).  So d3cold_delay has a different value only
if it's changed in a quirk or similar.

pci_acpi_optimize_delay() actually sets d3cold_delay to zero under
certain conditions, so your patch *will* cause a change of behavior.

Bottom line is, I think there's nothing to fix here.

Thanks,

Lukas