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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?yDbsie3R2/HSUHT1JDtzROhY31hBZWqXab3nbaoSnBhGzcZf6E5hATRHKeRB?= =?us-ascii?Q?JucYSjXMXHayMVOUDjeL0yyVCpnrA4ZgInHeIBx0RFjOUA1Dvd9mmNndzU9B?= =?us-ascii?Q?h6UR3bpB7cflusDqO42MKkmwpPZXmhnJJA2Nrh3yDPAGpMY8H8PrXnoQTAPW?= =?us-ascii?Q?2a+ewrOMaW/B7rLVJ0IcFrIFajAjrsInQcq2IjUdByad2RFsucCKich0gwhA?= =?us-ascii?Q?y8kRoktwrcqaU7AMFSKVcfx8hntX9o4bcbnnKGf1o/XuxYeLFWJdoEgguBrT?= =?us-ascii?Q?iHwjBi2vNnUesbrKPM7QKvA6/CSerYj7Bw6kZBJU5ROcAJw8BsVLgOR0rAcZ?= =?us-ascii?Q?Zh9okbR87H3MPKBqCJUnFuJGoRGtdAv8O1/zr4d1jWBeTFiTTGPbZ3M1bk3t?= =?us-ascii?Q?c6fX9h6L3fpuiMs5Kx3+jEEEtWu0ulUlb2+jfswYxczm7vxtfzzfGpVgO6V/?= =?us-ascii?Q?SaqRg8Tvvw+iz+D5vmU05vydFdu2k7ZSr70ra5vZXyNrFrmyouBk+OY7MqlR?= =?us-ascii?Q?MylP8mVTggda/byY58VBUbvFNoV67YRVpl/tnXxO3yNn7hc4KElThjr17k2k?= =?us-ascii?Q?cUHFol+qUEHDsyTwQfwnd6IMfjlfFoyHHRWdFCGSSLlkybGLW0s/KohjvF8O?= =?us-ascii?Q?T287/dFgjvm53goQbplppyfExaTsns29jaFRUu5+/MAfTxREIrNvsq0+UWfS?= =?us-ascii?Q?wuElYXAGrP91OAf6wb9U3wfrOasXx5soBMcF3fCIxWEEwQq53NoHyIaIwo5F?= =?us-ascii?Q?24K9k54JHwPq5Q/PzX5l87QETpc2Iarp+TjLlNW2UYHthqEU+JiBG4p0oyxD?= =?us-ascii?Q?iWv+HhK6ORC+XqfHJiXjYUnUyCgbWZvasfRpFiz3vTJG76fHCxIMlN9Ux+Jo?= =?us-ascii?Q?rRSYNYU31uw7I7ODT3vNPu0RG6nES0mH+vCFtPVUrWBhPc1oXo60UNWkM8OE?= =?us-ascii?Q?6mOhyHw5X8M7lO7/arty4sdNQGhlMEYINRr8D0ysxBEsC/hVbHt33Wz3rqb6?= =?us-ascii?Q?L9EMT/C7rUVhrfKqbHXuMB+ZijhYmT2cOFbTICcdr9pr7pBeKcDzjamfggsc?= =?us-ascii?Q?4W+3aQ4XmZbYPhN9RYLyQd0sie7zr+6303y3IQwfFlrG9rTlyaRGRZ3XttFh?= =?us-ascii?Q?tDyWoCWmV9N/kTe91pmIfELAA2EEvajkHCWatUPFzmvvHrJghFYv6ulgCi8V?= =?us-ascii?Q?K5+uRE6A45rkF2oISytzrqIJ/s0Qhb13/vk+tsyaWKf1x4MMDt4QIXLq3nd8?= =?us-ascii?Q?vO2QljSj50ajFclwkfYX5mNZ/WDm244W8XUU2bJB7pv7kfijbkAcCm+V139F?= =?us-ascii?Q?U9DllXLkgqiKoLFqDh8VHT6uovmphpOkNPtkDe3e2W6gkw3e/EEQduoOpT0Z?= =?us-ascii?Q?ihtxGYmi2HvZwWLqG9irrgeVrGQKoxHEYxHGoJfT7n1jUJVsEL3BcmFdgKbY?= =?us-ascii?Q?SpQcS53vctX6ESGovq6Jci+a7A5BrwRiXffuaBBj2LvMG4xI4sVK/Dx502gD?= =?us-ascii?Q?GQiXpgHcuryE883E/y2Aj0OxJez8rwABujDBVa8L0gId5bHh+hEWtVFwXilb?= =?us-ascii?Q?+tbYnfZ3K4evQ3+m8/Qp/5bvMfzfO3FSoAV2AHqf?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d7378159-28c8-4c56-b86c-08ddaf44538b X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 15:16:55.5499 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YuSzLsZRLY4eL4gibP6iz+C7IhH8SzE8YAM+pL+E3eGSEf1fCyW1aEehailNav53ypfIGWa4en9cxSHbJD/Ong== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8394 On Wed, Jun 18, 2025 at 11:21:03PM +0800, Hans Zhang wrote: > i.MX6 PCIe driver contains multiple read-modify-write sequences for > link training and speed configuration. These operations manually handle > bit masking and shifting to update specific fields in control registers, > particularly for link capabilities and speed change initiation. > > Refactor link capability configuration and speed change handling using > dw_pcie_clear_and_set_dword(). The helper simplifies LNKCAP modification > by encapsulating bit clear/set operations and eliminates intermediate > variables. For speed change control, replace explicit bit manipulation > with direct register updates through the helper. > > Adopting the standard interface reduces code complexity in link training > paths and ensures consistent handling of speed-related bits. The change > also prepares the driver for future enhancements to Gen3 link training > by centralizing bit manipulation logic. > > Signed-off-by: Hans Zhang <18255117159@163.com> > --- Reviewed-by: Frank Li > drivers/pci/controller/dwc/pci-imx6.c | 26 ++++++++++---------------- > 1 file changed, 10 insertions(+), 16 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 5a38cfaf989b..3004e432f013 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -941,7 +941,6 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > struct imx_pcie *imx_pcie = to_imx_pcie(pci); > struct device *dev = pci->dev; > u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > - u32 tmp; > int ret; > > if (!(imx_pcie->drvdata->flags & > @@ -956,10 +955,9 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > * bus will not be detected at all. This happens with PCIe switches. > */ > dw_pcie_dbi_ro_wr_en(pci); > - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > - tmp &= ~PCI_EXP_LNKCAP_SLS; > - tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); > + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, > + PCI_EXP_LNKCAP_SLS, > + PCI_EXP_LNKCAP_SLS_2_5GB); > dw_pcie_dbi_ro_wr_dis(pci); > > /* Start LTSSM. */ > @@ -972,18 +970,16 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > > /* Allow faster modes after the link is up */ > dw_pcie_dbi_ro_wr_en(pci); > - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > - tmp &= ~PCI_EXP_LNKCAP_SLS; > - tmp |= pci->max_link_speed; > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); > + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, > + PCI_EXP_LNKCAP_SLS, > + pci->max_link_speed); > > /* > * Start Directed Speed Change so the best possible > * speed both link partners support can be negotiated. > */ > - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > - tmp |= PORT_LOGIC_SPEED_CHANGE; > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); > + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, > + 0, PORT_LOGIC_SPEED_CHANGE); > dw_pcie_dbi_ro_wr_dis(pci); > > ret = imx_pcie_wait_for_speed_change(imx_pcie); > @@ -1295,7 +1291,6 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > struct imx_pcie *imx_pcie = to_imx_pcie(pci); > - u32 val; > > if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_8GT_ECN_ERR051586) { > /* > @@ -1310,9 +1305,8 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > * to 0. > */ > dw_pcie_dbi_ro_wr_en(pci); > - val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > - val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); > + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, > + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0); > dw_pcie_dbi_ro_wr_dis(pci); > } > } > -- > 2.25.1 >