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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?iJPfK5E85mNN2l0z9MmP9bGCfCKXOtdvobpmEE0P2rqXCzxRrcswhIIHsyQm?= =?us-ascii?Q?YyJZhA5q/Jfr13uLjSDknf4ovsuxkRvaMqKwF/t/1atwvMLUp8DAqfzg+uQo?= =?us-ascii?Q?E/YCdMr51y9+KDmCCUGf4Mc1kR+Nt6ktVj7/tYbqJh+hnBqfSOz4bwjF/E5Z?= =?us-ascii?Q?ku2pLqXViGqRNtqtvVkoppaSax5dgZFGQ7D/MsrjMarFeRwZZ3/NDx+yAhPw?= =?us-ascii?Q?FJZ7kMY8QJFkMIyWBq4cRM+phF/pPZCcUFbhWMVZEjkReJTKXSSBFskyLxhI?= =?us-ascii?Q?X6fuJKguKTCMXUjT8hKRBeMJTtg1A6/QQkoI8R41aF6nesv7M0VjaTqNQOdw?= =?us-ascii?Q?EFKxhxTkvNF9u9SMYCKcb060m7p0TKsRkpOan39cQnc3i0M4oLiuWp0nFdkv?= =?us-ascii?Q?6qtR9tJH1Wqa+3s/WqHKbwxCNARRD+HGEeUzhfqlHKDsC6RRpDBhBQnjL4f5?= =?us-ascii?Q?pKsoPeP7b5cPlkbUXqr4dZ5GP7VLzNz/cBbMBpiSfzdtkfPaMZE54pnHh8YB?= =?us-ascii?Q?a3Mq3WTqqWjBQGRWsL7g+Un1XwdR/wxSltvpjhBggBF8zCVtKHfKV0eB7hay?= =?us-ascii?Q?Ra0hi+jYiuKMWIZPw8ZT955T34xD635oU7wSb0dzRNmk43tiPU+PwKQVHiCW?= =?us-ascii?Q?cq7vzALkE3nJ26DOUuXbigpSb2YvYylto9srbQcxAV0zpsuFaLMrlmxdVYq9?= =?us-ascii?Q?lWZajb7vNhaGg7Be34zpUXbqeTBRzIRH7d0/qVg7ME7K9573PcEq0DkUmNid?= =?us-ascii?Q?bmQUSzOfxSAM1Rud8EpiHY1mIkfqo5AiDcN6o9zwo12dp7+rG+64C1p7ts53?= =?us-ascii?Q?d2gOt6CB7zyqGa0LqHcYN3ogAQf7Np6HUmpWW+E/03pP9ROJizE1zg0b2NtD?= =?us-ascii?Q?d4fh0qm1SEe7sLI4jkTIAG1+G/8I9TAMaio3ueX9Qk1WU1qJaz6Lj5HcjP7W?= =?us-ascii?Q?AbdDezOGY6Wnbx2y/eYiBOgatuBu+ImoVvEYAaG7zsBghxPfPY1wrTR2O3I3?= =?us-ascii?Q?rWDApi/KwLPrhNpRehrwPMl3hmUUm+l8qM/FH166UKfWklLbmkNyajqDwiFs?= =?us-ascii?Q?q9vV/qR5Cn+pudt+S22tPCxj3OgmxtUn1nnvrrgOlecPceWRAD/FN5+FqAhZ?= =?us-ascii?Q?CsL/8IqHHOpiC4vGZnTfHt9XKvMWRSLEi8GdqaZVblwX+loP8THXE3bu7lEo?= =?us-ascii?Q?2Fr31O3cki8Cao0/ECj2E+UgSdF4tWV0VjQM8yg/97keAfIV1srZmzGGVKoO?= =?us-ascii?Q?DcsF5dxzTW/KXZY4zCAN+AcZGsvTUjtD//TOK+2VpmIc1IXdxuEXO379kDo7?= =?us-ascii?Q?AMvF+SpMFzXirQ9pxpku9wlCXiienj8cbTzxH3GLX/0KGSiicrdrCEGDnPZc?= =?us-ascii?Q?hSbIi2b13PL39MYhSWmcb9LKDATdjix+heMcgPTEk1FdEBNBmsjgsCQXOiOq?= =?us-ascii?Q?WEZHf8BsvcJIuyVhiaZA27yMe5omuaaVGMhFUIU9AMh11ad7EogQEqEkom0I?= =?us-ascii?Q?NSfpTJeGhFoEbC3eMUNqUmEQD0FhIBnmj03LZd9SHU2N7NcAd8thgbAAJNhg?= =?us-ascii?Q?mUJeXcnakQmkebmozfNU7SG3hs7T3OZAEkgRFdUp?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 05bf3ae0-cdf4-4041-88d7-08ddb33f3453 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2025 16:50:20.0741 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BRWU5LgCs1eNf5PU3s1Bc24cXiajbVkhdqRO6b6BXaj/JJhxULa54q8PdDUFlsB3EqrgQqOk6dG+jKL8ABKO7g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR04MB7143 On Tue, Jun 24, 2025 at 11:35:36AM +0100, James Clark wrote: > In target mode, the host sending more data than can be consumed would be > a common problem for any message exceeding the FIFO or DMA buffer size. > Cancel the whole message as soon as this condition is hit as the message > will be corrupted. > > Only do this for target mode in a DMA transfer because we need to add a > register read. "We need to add a register read" is not reason. Add checking FIFO error status at target mode in a DMA transfer since PIO mode already do it. It help catch some host mode ... > In IRQ and polling modes always do it because SPI_SR was > already read and it might catch some host mode programming/buffer > management errors too. > > Signed-off-by: James Clark > --- > drivers/spi/spi-fsl-dspi.c | 28 +++++++++++++++++++++++++++- > 1 file changed, 27 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c > index 58881911e74a..16a9769f518d 100644 > --- a/drivers/spi/spi-fsl-dspi.c > +++ b/drivers/spi/spi-fsl-dspi.c > @@ -560,12 +560,24 @@ static void dspi_rx_dma_callback(void *arg) > complete(&dma->cmd_rx_complete); > } > > +static int dspi_fifo_error(struct fsl_dspi *dspi, u32 spi_sr) > +{ > + if (spi_sr & (SPI_SR_TFUF | SPI_SR_RFOF)) { > + dev_err_ratelimited(&dspi->pdev->dev, "FIFO errors:%s%s\n", > + spi_sr & SPI_SR_TFUF ? " TX underflow," : "", > + spi_sr & SPI_SR_RFOF ? " RX overflow," : ""); > + return -EIO; > + } > + return 0; > +} > + > static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) > { > size_t size = dspi_dma_transfer_size(dspi); > struct device *dev = &dspi->pdev->dev; > struct fsl_dspi_dma *dma = dspi->dma; > int time_left; > + u32 spi_sr; > int i; > > for (i = 0; i < dspi->words_in_flight; i++) > @@ -614,7 +626,8 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) > > if (spi_controller_is_target(dspi->ctlr)) { > wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete); > - return 0; > + regmap_read(dspi->regmap, SPI_SR, &spi_sr); > + return dspi_fifo_error(dspi, spi_sr); > } > > time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, > @@ -1069,6 +1082,10 @@ static void dspi_poll(struct fsl_dspi *dspi) > > if (spi_sr & SPI_SR_CMDTCF) > break; > + > + dspi->cur_msg->status = dspi_fifo_error(dspi, spi_sr); > + if (dspi->cur_msg->status) > + return; Although fifo error may happen after you check, it may reduce some possilbity and catch some problems. Frak > } while (--tries); > > if (!tries) { > @@ -1085,6 +1102,7 @@ static void dspi_poll(struct fsl_dspi *dspi) > static irqreturn_t dspi_interrupt(int irq, void *dev_id) > { > struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; > + int status; > u32 spi_sr; > > regmap_read(dspi->regmap, SPI_SR, &spi_sr); > @@ -1093,6 +1111,14 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id) > if (!(spi_sr & SPI_SR_CMDTCF)) > return IRQ_NONE; > > + status = dspi_fifo_error(dspi, spi_sr); > + if (status) { > + if (dspi->cur_msg) > + WRITE_ONCE(dspi->cur_msg->status, status); > + complete(&dspi->xfer_done); > + return IRQ_HANDLED; > + } > + > dspi_rxtx(dspi); > > if (!dspi->len) { > > -- > 2.34.1 >