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[96.255.20.42]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-702c4d5ad73sm2155396d6.92.2025.07.03.12.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jul 2025 12:40:23 -0700 (PDT) Date: Thu, 3 Jul 2025 15:40:21 -0400 From: Gregory Price To: Dave Jiang Cc: "Fabio M. De Francesco" , linux-cxl@vger.kernel.org, Davidlohr Bueso , Jonathan Cameron , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] cxl: docs/driver-api/conventions resolve conflicts btw CFMWS, LMH, ED Message-ID: References: <20250623152923.1048525-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jul 01, 2025 at 08:23:57AM -0700, Dave Jiang wrote: > > > On 6/23/25 12:19 PM, Gregory Price wrote: > > On Mon, Jun 23, 2025 at 05:29:02PM +0200, Fabio M. De Francesco wrote: > >> Add documentation on how to resolve conflicts between CXL Fixed Memory > >> Windows, Platform Memory Holes, and Endpoint Decoders. > >> > >> Signed-off-by: Fabio M. De Francesco > > > > I won't block a doc update on a suggestion so > > > > Reviewed-by: Gregory Price > > > >> +Platform Firmware (BIOS) might reserve part of physical addresses below > >> +4 GB (e.g., the Low Memory Hole that describes PCIe memory space for MMIO > >> +or a requirement for the greater than 8 way interleave CXL regions starting > >> +at address 0). In that case the Window Size value cannot be anymore > >> +constrained to the NIW * 256 MB above-mentioned rule. > > > > It might be nice to have a diagram that explains this visually, as it's > > difficult for me to understand the implications through words alone... > > +1 on request for diagram to explain. We should try to document this issue as clearly as possible. Thank you. > At the very least, it would be nice to have an explicitly example that explains the expected cfmws/decoder configurations that are valid but "technically" violate the spec I *think* this basically boils down to "CFMWS size is not aligned, but all the decoders it targets are"? If I understand this correctly? > > > > which is likely why the conflict exists in the first place :] > > > > ~Gregory >